Table A.20 shows the tie-off signals.
Indicates whether the system supports coherent page table walks.
This information is also shown in the SMMU_IDR0. The signal value does not have any impact on the way the MMU-500 generates accesses. Instead, the signal value is generated by the system integrator and it is used to check the coherency of the system to which the TCU is connected.
You can specify one of the following options:
When this signal is HIGH, the MMU-500 bypasses architectural clock gates. This signal is used in the DFT test mode. You can specify one of the following values:
When this signal is set, Non-secure accesses can access the integration registers. See Integration registers
When this signal is HIGH, you must tie the spniden input signal LOW.
Specifies whether the MMU-500 can generate barriers or not. You can specify one of the following options:
|dftmcphold||I||1||This signal must be tied HIGH when TCU half clock configuration is selected to enable scan testing.|
This signal indicates the reset value of the SACR.NORMALIZE bit. You can specify one of the following options: