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2.2.2. TBU interfaces

The MMU-500 supports the following TBU interfaces:

ACE-Lite interfaces

The MMU-500 uses the ACE-Lite interfaces to receive and forward transactions after a translation.

An AXI3 or AXI4 bus can be connected to this interface with certain limitations as described in AXI3 and AXI4 support.

When an ACE-Lite interface is used, the MMU-500 generates barrier transactions and updates attributes of input barrier transactions. Barrier transactions guarantee the ordering and observation of transactions in a system.

For more information on barrier transactions, see the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite.

AXI slave interface

The MMU-500 supports only the ACE-Lite slave interface for every TBU. To connect to an AXI3 or AXI4 interface, you must:

  • Tie the extra ACE-Lite signals to their inactive values.

  • Tie the sysbardisable_<tbuname> signal HIGH.

The ACE-Lite slave interface, with _s suffix, drives the untranslated address to the TBU. You must connect pin-to-pin the read address, write address, read data, write data, and buffered write response channels of the ACE-Lite slave interface to an ACE-Lite master interface. In a system, the master interface can be the AXI bus infrastructure output or the output of a bridge that converts another bus protocol to AXI.

AXI master interface

The MMU-500 supports only the ACE-Lite master interface for every TBU. You must tie the extra ACE-Lite signals to their inactive values and the sysbardisable_<tbuname> signal to HIGH to use AXI3 or AXI4 master interfaces.

The ACE-Lite master interface, with _m suffix, drives the translated address to the downstream slave. You must connect pin-to-pin the read address, write address, read data, write data, and buffered write response channels to the corresponding ACE-Lite slave interface.

If the MMU-500 is configured to support a dedicated interface for PTWs, you must connect the read address and read data channels of the slave interface associated with the PTWs to the MMU-500 PTW channel. In this configuration, the PTW channel contains the _ptw suffix. For example, araddr_ptw and acaddr_ptw.

TBU barrier support

The TBU in the MMU-500 receives, passes on, and generates barriers of its own.

The MMU-500 generates a DSBSYS barrier on its own, after ensuring that all invalidation-related transactions are initiated when sysbardisable_<tbuname> is LOW, and on receiving one of the following:

  • The SYNC message received on the programming interface.

  • The DVM SYNC message.

For more information on SYNC and DVM SYNC messages, see the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite.

Sideband interface

The sideband interface provides associated information, such as data byte, transfer, packet, or frame-based information along with the ACE-Lite interface. See Sideband signals.

Note

The StreamID and security state determination are associated with the ACE-Lite slave interface to each TBU.

StreamID interface

The StreamID interface is a sideband interface for the MMU-500 TBU slave interface. It provides additional information about the source of the incoming transaction. This information is used to map the transaction to a particular context for translation.

The MMU-500 samples signals in the interface along with each valid address transaction.

See StreamID.

Security State Determination (SSD) interface

The SSD interface is a sideband interface for the MMU-500 TBU slave interface. It provides information about the security state of a transaction.

The MMU-500 samples signals in this interface along with each valid address transaction, in a similar manner to the StreamID.

See Security determination.

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