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1.7. Test features

The MMU-500 includes clock gating circuitry that can be used to enable the clock during MMU-500 testing.

The Design for Test (DFT) port, dftclkenable, allows bypassing of architectural clock gates during a DFT shift.

The DFT port, dftmcphold, is used to bypass a clock divider, when you select the half clock mode.

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