The SMMU_PER characteristics include:
Checks for parity errors in TCU and TBU RAMs.
Available in all MMU-500 configurations.
Figure 3.16 shows the bit assignments.
Table 3.28 shows the bit assignments.
|[15:8]||PER_TCU||Parity errors found in TCU RAMs. This bit field saturates after reaching the maximum value.|
|[7:0]||PER_TBU||Parity errors found in TBU RAMs. This bit field saturates after reaching the maximum value.|
The TBU micro TLB, the TCU macro TLB and the walk cache RAMs support single bit error detection and invalidation on error detection. The TCU MFIFO RAM supports the single bit error detection and correction.