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2.2.3. Common interfaces

The MMU-500 supports the following interfaces that are common to TBUs and the TCU:

Low-power interface for clock gating and power control

The MMU-500 contains Q-channel low-power interfaces that enable:

  • Power gating of the TBU module.

  • Clock gating of the TBU module.

  • Clock gating of the TCU module.

You can control the power-control interfaces at the system level by a system power-control module. Alternatively, if there is no system control block, you must tie the qreqn_* inputs HIGH, and can leave the outputs, qacceptn_* and qactive_* unconnected.

The MMU-500 never denies a powerdown request on any Q-channel, and so you must tie LOW the qdeny_* input to the system power controller.

The TCU module must be powered up before, or at the same time as, any TBU module is powered up. The TCU module must remain powered up while any TBU module is powered up.


The low-power interface signals are not synchronized. The system must provide the synchronous signals to the MMU-500.

The MMU-500 provides a Q-channel low-power interface for clock gating support. This interface is used as follows:

  • The TBU and TCU have dedicated low-power Q-channel interfaces for clock gating:

    • qreqn_tbu_<tbuname>_cg, qacceptn_tbu_<tbuname>_cg, and qactive_tbu_<tbuname>_cg.

    • qreqn_tcu, qacceptn_tcu, and qactive_tcu.

  • The TBU and the clock or power bridge each have a dedicated Q-channel interface for entering the powerdown state:

    • qreqn_tbu_<tbuname>_pd and qacceptn_tbu_<tbuname>_pd.

    • qreqn_pd_slv_br_<tbuname> and qacceptn_pd_slv_br_<tbuname>.

    • qreqn_pd_mst_br_<tbuname> and qacceptn_pd_mst_br_<tbuname>.

  • The clock or power bridge contains the following qactive signals:

    • The qactive_br_tbu_<tbuname> signal for handling the cross-boundary clock wakeup to wake up the TBU clock.

    • The qactive_br_tcu_<tbuname> signal for handling the cross-boundary clock wakeup to wake up the TCU clock.

Figure 2.3 shows the possible clock and power domains of the MMU-500.

Figure 2.3. Clock and power domains of the MMU-500

Figure 2.3. Clock and power domains of the MMU-500

Figure 2.4 shows that TBU0 and TCU share a common clock or power domain. The TCU page table walk read channel shares the AXI interface with the TBU0.

Figure 2.4. TBU0 and TCU sharing a common clock or power domain

Figure 2.4. TBU0 and TCU sharing a common clock
or power domain

The full clock to half clock configuration feature shown in Figure 2.3 and Figure 2.4 is also applicable to:

  • Interrupts.

  • Programming interfaces.

  • PTW interfaces.

If you configure the TCU PTW interface to be shared with the TBU0 master interface by disabling the PTW has a separate AXI port configuration parameter, a multiplexer is instantiated in the design. You can use the multiplexer to share the ACE-Lite interface of TBU0 with the PTW interface generated by the TCU, provided you ensure that the TBU0 data width is the same as that of the TCU.

In this shared configuration, TBU and TCU still have two separate LPI interfaces for clock gating. Consequently, when TBU0 is clock gated, you can still see accesses coming from the TCU PTW interface and being output from the shared TBU0 master interface.

The MMU-500 supports the half clock feature as shown in Figure 2.3 and Figure 2.4 depending on the specified configuration.

For more information about the Q-channel low-power interface, see the Low Power Interface Specification, ARM® Q-Channel and P-Channel Interfaces.

Performance interface

This interface contains the input signal spniden that enables the counting of events resulting from Secure translations, and contains an event output interface that provides updates from each TBU to the performance counters.

See Performance event signals and Authentication interface signal.

Tie-off signal interface

This interface provides configuration information about AXI or ACE-Lite interface operations and page table walk coherency. See Tie-off signals.

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