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2.2.1. TCU interfaces

The MMU-500 supports the following TCU interfaces:

Programming interface

The MMU-500 requires a programming interface to permit the software to configure the controller and to initialize the memory devices. For information about using the 64-bit AXI4 programming interface, see Modes of operation and execution.

The MMU-500 provides 32-bit address buses, awaddr_prog[31:0] and araddr_prog[31:0], but it only uses bits that are dependent on the number of context selection as shown in Table 2.1.

Table 2.1. Bit dependency on number of context selection
Number of contextBits

The MMU-500 ignores bits[1:0], because the smallest accesses allowed to its internal registers are word accesses.

This interface operates at the same frequency as the TCU clock.


If half-clock configuration is selected, the TCU core runs at half the speed compared to this interface.


This interface provides global, per-context, and performance interrupts. See Interrupt signals.

DVM interface

The AC channel of the ACE-Lite interface of the MMU-500 is connected to the CCI-driven AC channel or to the ACE-compatible slave interface that supports DVM messaging. ARM recommends that you use the DVM channel for TLB maintenance operations. If the system cannot access the DVM channel, the acvalid signal must be tied LOW, and the programming interface can be used for TLB maintenance operations.

When you configure the MMU-500 to provide a dedicated AXI channel to perform PTWs, the AC channel must be part of the PTW channel.


If a dedicated channel is not configured, use the TBU0 AXI interface suffix, and ensure that it is connected to the TCU.

This interface supports the following:

AC channel (address channel)

The 44-bit wide AC channel is connected to the TCU.


The CD channel (data channel) is not connected to the MMU-500.

PTW interface

In the MMU-500, there can be a dedicated interface that provides access to memory for page table walks.

If the MMU-500 is configured to support a dedicated interface for PTWs, you must connect the read address and read data channels of the slave interface associated with the PTWs to the MMU-500 PTW channel. In this configuration, the PTW channel contains the _ptw suffix. For example, araddr_ptw and acaddr_ptw.


  • The write interface on the dedicated PTW interface is not used.

  • If the MMU-500 is configured not to support a dedicated interface for PTWs, PTWs are performed on the ACE-Lite interface connected to TBU0.

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