Figure 1.2 shows the MMU-500 in an example ARM processor and CoreLink Cache Coherent Interconnect-400 (CCI-400) system, performing address translation functions for multiple masters including a GPU.
In the example system, transactions sent by the GPU master are received by the TBU on its slave interface to search for a TLB hit. On a miss, the TBU interacts with the TCU through its AXI stream interface, and initiates a page table walk. On receiving the page table entry or a TLB hit, the TBU then forwards the transaction to its master interface after the pending translation based on the page entry.
If an AXI3 or AXI4 interface is connected to an ACE-Lite port, then the unused ACE-Lite signals must be tied off to the values shown in Table 2.2.