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3.1. About this programmers model

The following information applies to the MMU-500 registers:

  • Registers are implemented according to the ARM® System Memory Management Unit Architecture Specification with the security extensions implemented in the MMU-500 as follows:

  • Unless otherwise stated in the accompanying text:

    • Do not modify undefined register bits.

    • Ignore undefined register bits on reads.

    • All register values are unknown on reset unless otherwise stated.

  • The access types of the MMU-500 registers are as follows:

    RAO

    Read-As-One.

    RAO/SBOP

    Read-As-One, Should-Be-One-or-Preserved on writes.

    RAO/WI

    Read-As-One, Writes-ignored.

    RAZ

    Read-As-Zero.

    RAZ/SBZP

    Read-As-Zero, Should-Be-Zero-or-Preserved on writes.

    RAZ/WI

    Read-As-Zero, Write-ignored.

    RO

    Read-only.

    RW

    Read and write.

    SBO

    Should-Be-One.

    SBOP

    Should-Be-One-or-Preserved.

    SBZ

    Should-Be-Zero.

    SBZP

    Should-Be-Zero-or-Preserved.

    UNK

    Unknown.

    WI

    Write-ignored.

    WNR

    Write-not-read.

    WO

    Write-only.

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