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3.2. Modes of operation and execution

The MMU-500 provides a 64-bit AXI4 programming interface as per the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite. The interface restrictions are as follows:

  • A single combined acceptance depth is used for write and read channels.

  • All 32-bit register write accesses must:

    • Be one beat long.

    • Be used for a word-aligned location.

    • Be 32 bits wide.

    • Have all relevant write strobes set.

    If any of these conditions is not met, the MMU-500 ignores the transaction.

  • All 64-bit register write accesses must satisfy one of the following conditions:

    • Be one beat long, 64 bits wide, used for a double-word aligned location, and have all write strobes set.

    • Be two beats long, 32 bits wide, used for a double-word aligned location, and have all relevant write strobes set.

    • Be one beat long, 32 bits wide, used for a word aligned location, and have all relevant write strobes set.

    If any of these conditions is not met, the MMU-500 ignores the transaction.

  • The AXI4 programming interface does not log errors or issue error responses. It treats invalid accesses as either RAZ or WI.

  • The AXI4 programming interface ignores the AxBURST, AxLOCK, AxCACHE, AxQOS, AxREGION, and AxUSER signals.

  • If a master connected to the MMU-500 generates a FIXED-type burst, and if the translated domain is a shared DOMAIN (Inner-shared or Outer-shared), then the MMU-500 generates an Unsupported Upstream Transaction (UUT) fault.

    • For single-beat transfers, a master can generate an INCR type burst to avoid this problem.

    • For multi-beat transfers, the MMU-500 cannot avoid this problem, and the system must generate the ouput DOMAIN value as Non-shared or System-shared.

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