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3.9.2. Peripheral Identification registers

The characteristics of the SMMU_PIDR registers are:

Purpose

Bits[7:0] of the SMMU_PIDR 0-4 registers are used and bits[31:8] are reserved. The SMMU_PIDR 7-5 registers are reserved.

Configuration

Available in all MMU-500 configurations.

Usage constraints

There are no usage constraints.

Attributes

The peripheral identification registers are as follows:

Peripheral Identification register 0

Figure 3.19 shows the bit assignments.

Figure 3.19. SMMU_PIDR0 register bit assignments

Figure 3.19. SMMU_PIDR0 register bit assignments

Table 3.31 shows the bit assignments.

Table 3.31. SMMU_PIDR0 register bit assignments
BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:0]PartNumber00x81Middle and lower-packed BCD value of the device number [7:0].

Peripheral Identification register 1

Figure 3.20 shows the bit assignments.

Figure 3.20. SMMU_PIDR1 register bit assignments

Figure 3.20. SMMU_PIDR1 register bit assignments

Table 3.32 shows the bit assignments.

Table 3.32. SMMU_PIDR1 register bit assignments
BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:4]JEP106 identity code0xBJEP106 identity code.
[3:0]PartNumber10x4Upper packed-BCD value of the device number [11:8].

Peripheral Identification register 2

Figure 3.21 shows the bit assignments.

Figure 3.21. SMMU_PIDR2 register bit assignments

Figure 3.21. SMMU_PIDR2 register bit assignments

Table 3.33 shows the bit assignments.

Table 3.33. SMMU_PIDR2 register bit assignments
BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:4]Architecture Revision0x1Indicates ARM SMMU architecture v2.
[3]JEDEC0x1Always set, indicates that a JEDEC-assigned value is used.
[2:0]JEP106 identity code0x3JEP106 continuation code that identifies the designer. The value of 0x3 indicates ARM.

Peripheral Identification register 3

Figure 3.22 shows the bit assignments.

Figure 3.22. SMMU_PIDR3 register bit assignments

Figure 3.22. SMMU_PIDR3 register bit assignments

Table 3.34 shows the bit assignments.

Table 3.34. SMMU_PIDR3 register bit assignments
BitsName Reset valueDescription
[31:8]Reserved-Reserved.
[7:4]RevAnd0x0Manufacturer revision number. By default, this value is set to 0x0 (specified by ARM).
[3:0]Customer modified0x0Customer modified number. This value is set to 0x0 (specified by ARM).

Peripheral Identification register 4

Figure 3.23 shows the bit assignments.

Figure 3.23. SMMU_PIDR4 register bit assignments

Figure 3.23. SMMU_PIDR4 register bit assignments

Table 3.35 shows the bit assignments.

Table 3.35. SMMU_PIDR4 register bit assignments
BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:4]4KB Count

0x0

Reserved.
[3:0]JEP106 continuation code0x4JEP106 continuation code that identifies the designer. The value of 0x4 indicates ARM.

Peripheral Identification registers 5-7

Figure 3.24 shows the bit assignments.

Figure 3.24. SMMU_PIDR 5-7 register bit assignments

Figure 3.24. SMMU_PIDR 5-7 register bit assignments

Table 3.36 shows the bit assignments.

Table 3.36. SMMU_PIDR 5-7 register bit assignments
BitsName Reset valueDescription
[31:0]Reserved-Reserved

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