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3.4.4. Peripheral and component identification registers summary

Table 3.6 shows the peripheral and component identification registers in base offset order.

Table 3.6. Peripheral and component identification summary
NameTypeS or NSOffsetDescription
SMMU_PIDR4RONS/S0x0FD0Peripheral Identification registers
SMMU_PIDR5RONS/S0x0FD4
SMMU_PIDR6RONS/S0x0FD8
SMMU_PIDR7RONS/S0x0FDC
SMMU_PIDR0RONS/S0x0FE0
SMMU_PIDR1RONS/S0x0FE4
SMMU_PIDR2RONS/S0x0FE8
SMMU_PIDR3RONS/S0x0FEC
SMMU_CIDR0RONS/S0x0FF0Component Identification registers
SMMU_CIDR1RONS/S0x0FF4
SMMU_CIDR2RONS/S0x0FF8
SMMU_CIDR3RONS/S0x0FFC

Note

The peripheral and component identification registers can be accessed through the SMMU_GR0 register.

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