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A.2. AHB-Lite master interface signals

Table A.2 shows the AHB-Lite master interface signals.

Table A.2. AHB-Lite master interface signals
Signal nameDirectionDescription
HADDR[31:0]OutputSee the ARM® AMBA® 3 AHB-Lite Protocol Specification.
HBURST[2:0]
HMASTLOCK
HPROT[3:0]
HRDATA[DATA_WIDTH-1:0][a]Input
HREADY
HRESP
HSIZE[2:0]Output
HTRANS[1:0]
HWDATA[DATA_WIDTH-1:0][a]
HWRITE
Exclusive access signals:
EXREQ[b]Output

This is an address phase signal that indicates if a transfer is part of an exclusive transaction:

LOW

Non-exclusive transaction.

HIGH

Exclusive transaction.

During IDLE transfers EXREQ is LOW.

EXRESP[b]Input

This is a data phase signal. It indicates whether the exclusive request was granted or failed:

LOW

Exclusive access granted.

HIGH

Exclusive access failed.

EXRESP is only valid when EXREQ is HIGH in the address phase.

User sideband signals:
HAUSER[15:0][c]OutputThis is an address phase signal.
HRUSER[15:0][c]InputThis is a data phase signal that is only valid for read transfers when HREADY is HIGH.
HWUSER[15:0][c]OutputThis is a data phase signal that is only valid for write transfers.

[a] The signal width is configurable. See the ARM® CoreLink™ AXI4 to AHB-Lite XHB-400 Bridge Integration and Implementation Manual for information about signal widths that the XHB supports.

[b] Exclusive access signals are extensions to the AHB-Lite protocol. See Exclusive accesses.

[c] User sideband signals are extensions to the AHB-Lite protocol. See User sideband signals.


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