Table A.2 shows the AHB-Lite master interface signals.
|HADDR[31:0]||Output||See the ARM® AMBA® 3 AHB-Lite Protocol Specification.|
|Exclusive access signals:|
This is an address phase signal that indicates if a transfer is part of an exclusive transaction:
During IDLE transfers EXREQ is LOW.
This is a data phase signal. It indicates whether the exclusive request was granted or failed:
EXRESP is only valid when EXREQ is HIGH in the address phase.
|User sideband signals:|
|HAUSER[15:0][c]||Output||This is an address phase signal.|
|HRUSER[15:0][c]||Input||This is a data phase signal that is only valid for read transfers when HREADY is HIGH.|
|HWUSER[15:0][c]||Output||This is a data phase signal that is only valid for write transfers.|
[a] The signal width is configurable. See the ARM® CoreLink™ AXI4 to AHB-Lite XHB-400 Bridge Integration and Implementation Manual for information about signal widths that the XHB supports.