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Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A
ChangeLocationAffects

First release

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Table B.2. Differences between issue A and issue B
ChangeLocationAffects
Added text clarifying the use of CORECLKEN[N:0]Clock enablesAll revisions
Added text to end of section regarding interface signalsClock enablesAll revisions
Updated first bullet point and added second bullet pointResetsAll revisions
Updated first sentence of section L2 RAMs dynamic retentionState retention controlAll revisions
Added text regarding assertion of nCORERESET[N:0] and nCOREPRESETDBG[N:0] in multiprocessor device shutdown mode step 7.Power modesAll revisions
Changed ACTLR[3] from reserved to ASSEAuxiliary Control Registerr1p0

Updated functional description of bit FLT_END_ADDR

Table 4.74All revisions
Updated Usage constraints, fourth bullet pointL2 Control RegisterAll revisions
Changed L2CTLR[20] from reserved to SFENL2 Control Registerr1p0
Updated first bullet pointMemory typesAll revisions
Updated table row AWID[4:0] and ARID[4:0]Table 7.2 and Table 7.3All revisions
Revised text describing reset requirementsResetsAll revisions
Added timing requirement for logic state in powerup resetResetsAll revisions
Revised descriptionProcessor Wait for EventAll revisions
Revised descriptionEvent communication using WFE or SEVAll revisions
Updated MIDR.Variant for major revision 1Table 4.29r1p0
Added description of L2CTLR.IWINCTable 4.68All revisions
Revised description of implementation defined TEX encodingTable 5.1All revisions
Revised description of PLI instructionPLD, PLDW, and PLI instructionsAll revisions
Revised description of ACP errorACP requests All revisions
Corrected the Extended External input bus size and revised the descriptionTable 11.10All revisions

Table B.3. Differences between issue B and issue C
ChangeLocationAffects
Clarified state of clock enables during low-power stateClock enablesr1p0
Corrected figure Figure 9.8All revisions
Corrected reset value of MIDRTable 4.29r1p0
Updated description of CNTCLKENCNTCLKENAll revisions
Updated description of reset repeatersResetsAll revisions
Added note Individual processor shutdown modeAll revisions
Added register descriptionsDiagnostic control registersr1p1
Added register descriptionDiagnostic common control registerr1p1
Corrected reset value HSCTLR[21] in figureFigure 4.28All revisions
Corrected figureFigure 9.10All revisions
Updated description of PCLKENDBGClock enablesr1p1
Updated figureFigure 2.6r1p1
Updated figureFigure 2.7r1p1

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