You copied the Doc URL to your clipboard.

A.10. DFT signals

The table below lists signals related to test mode.

Table A.29. DFT signals

Reset bypass to disable internal generated reset for testing (for example ATPG).

Make WIC latch transparent.

DFTCGENCPU0Input1Clock gating bypass to disable internal clock gating for testing. This signal is used to ensure safe shift where the clock is forced on during the shift mode.

Was this page helpful? Yes No