The SSE-100 contains the following components:
A Cortex-M3 processor:
Bit-banding enables using standard instructions to read or modify of individual bits. The default implementation does not include bit banding.
Eight MPU regions (optional)
NVIC providing deterministic, high-performance interrupt handling with a configurable number of interrupts.
Wakeup Interrupt Controller (WIC) with configurable number of WIC lines (optional). This is a latch-based WIC implementation, and not the standard Cortex-M3 WIC. See the ARM® CoreLink™ SSE100 Subsystem Implementation and Integration Manual for more information.
Little-endian memory addressing only (for compatibility with eFlash controller and eFlash cache).
For more information see the ARM® Cortex®-M3 Processor Technical Reference Manual.
The Cortex-M3 has a Processor Integration Layer (PIL) to simplify integration of the SSE-100 into a multiprocessor system with a SoC-level CoreSight™ subsystem.
Configurable Debug and Trace as either:
Stand-alone system with a TPIU and a SWJ-DP.
Full CoreSight integration over a DAP and the ATB buses.
Multilayer AMBA AHB-Lite interconnect:
Low-latency interconnect bus matrix.
Two AHB-Lite initiator expansion ports for external AHB masters.
Two AHB-Lite target expansion ports for external AHB slaves.
Eleven APB4 target expansion ports (each with 4KB address space) to connect APB peripherals.
Memory system, consisting of:
Integrated eFlash cache with configurable cache size from 512bytes to 8KB. The cache is two-way set associative instruction cache with a four-word cache line.
Integrated eFlash controller for TSMC 55 ULP-TV2 eFlash.
The SSE-100 can be easily modified to replace the supplied eFlash controller if a different eFlash technology is used in the SoC, but the warranty is void if the SSE-100 is changed.
Static memory (configurable as one to four 32KB banks) is provided in the example integration layer.
eFlash memory (banked as 2×128KB or 2×256KB) is provided in the example integration layer.
Two APB timers:
Interrupt generation when the counter reaches 0.
Each timer has an TIMERnEXTIN signal that can be used as an enable or external clock.
Configurable privileged access mode.
Cordio BT4 Radio component (optional).
Fully integrated Bluetooth Smart controller subsystem IP block.
Radio transceiver, baseband, integrated link layer (LL) controller.
LL firmware up to the Host Controller Interface (HCI).
Delivered as a hard macro (55nm TSMC) with a synthesizable integration wrapper.
The Cordio BT4 IP is not provided with the SSE-100, and must be separately licensed from ARM.
A third-party Bluetooth solution can be connected to the AHB expansion ports, but that requires customized software and firmware to support the product.
The reference system contains the peripherals required to support a rich OS. The components highlighted in Figure 1.3 are not provided by the SSE-100. Other peripherals not included in the SSE-100 might be required for specific application areas.