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3.3.3. Register summary

Table 3.4. APB register map for eFlash controller
Register nameTypeWidthReset valueAddress offsetDescription
IRQ_SET_ENARW320x000000000x1000IRQ_SET_ENA register
IRQ_CLR_ENARW320x000000000x1004IRQ_CLR_ENA register
IRQ_SET_STATUSRW320x000000000x1008IRQ_SET_STATUS register
IRQ_CLR_STATUSRW320x000000000x100CIRQ_CLR_STATUS register
IRQ_MASKED_STATUSRO320x000000000x1010IRQ_MASKED_STATUS register
CTRLRW320x000000000x1014CTRL register
STATUSRO320x000000000x1018STATUS register
CONFIG0RW320x0008003F0x101CCONFIG0 register
CONFIG1RW320x000800000x1020CONFIG1 register
CONFIG2RW320x000800000x1024CONFIG2 register
WADDRRW320x000000000x1028WADDR register
WDATARW320x000000000x102CWDATA register
EFUSERO320x000000000x1030EFUSE register
HWPARAMS0RO320x000020110x1034HWPARAMS0 register
HWPARAMS1RO320x0000003F0x1038HWPARAMS1 register
HWPARAMS2RO320x000000000x103CHWPARAMS2 register
HWPARAMS3RO320x000000000x1040HWPARAMS3 register
PIDR4RO320x000000140x1FD0Product ID Register, PIDR4
PIDR5RO320x000000000x1FD4Product ID Register, PIDR5
PIDR6RO320x000000000x1FD8Product ID Register, PIDR6
PIDR7RO320x000000000x1FDCProduct ID Register, PIDR7
PIDR0RO320x000000300x1FE0Product ID Register, PIDR0
PIDR1RO320x000000B80x1FE4Product ID Register, PIDR1
PIDR2RO320x0000000B0x1FE8Product ID Register, PIDR2
PIDR3RO320x000000000x1FECProduct ID Register, PIDR3
CIDR0RO320x0000000D0x1FF0Component ID Register, CIDR0
CIDR1RO320x000000F00x1FF4Component ID Register, CIDR1
CIDR2RO320x000000050x1FF8Component ID Register, CIDR2
CIDR3RO320x000000B10x1FFCComponent ID Register, CIDR3

IRQ_SET_ENA register

Enables, or reads the enable state of interrupts.

RW register at offset 0x1000.

For the non-reserved bits:

  • On reads:

    • 0: interrupt disabled.

    • 1: interrupt enabled.

      If not masked, a hardware interrupt is generated if the corresponding bit of the IRQ_STATUS register is set.

  • On writes:

    • 0: no effect.

    • 1: enable interrupt.

Table 3.5. IRQ_SET_ENA register
BitsNameDescriptionAccessReset
[31:3]-ReservedRO, RAZ0
[2]NEXT-RW0
[1]TIMEOUT-RW0
[0]READY-RW0

IRQ_CLR_ENA register

Disables, or reads, the enable state of interrupts.

RW register at offset 0x1004.

For the non-reserved bits:

  • On reads:

    • 0: interrupt disabled.

    • 1: interrupt enabled.

      If not masked, a hardware interrupt is generated if the corresponding bit of the IRQ_STATUS register is set.

  • On writes:

    • 0: no effect.

    • 1: disable interrupt.

Table 3.6. IRQ_SET_ENA register
BitsNameDescriptionAccessReset
[31:3]-ReservedRO, RAZ0
[2]NEXT-RW0
[1]TIMEOUT-RW0
[0]READY-RW0

IRQ_SET_STATUS register

Shows the current raw status of interrupts or sets the status of interrupts.

RW register at offset 0x1008.

For the non-reserved bits:

  • On reads:

    • 0: interrupt not pending.

    • 1: interrupt pending.

  • On writes:

    • 0: no effect.

    • 1: sets the state of the interrupt to pending.

Table 3.7. IRQ_SET_STATUS register
BitsNameDescriptionAccessReset
[31:3]-ReservedRO, RAZ0
[2]NEXTThis interrupt is set by hardware during word-write operation whenever hardware is ready to accept the next word.RW0
[1]TIMEOUTThis interrupt is set by hardware when any row-write operation is finished by hardware as a result of software not clearing the NEXT interrupt within the specified time.RW0
[0]READYThis interrupt set by hardware when any word-write, row-write, page-erase, mass-erase operation finishes.RW0

IRQ_CLR_STATUS register

Shows the current raw status of interrupts or clears the status of interrupts.

RW register at offset 0x100C.

For the non-reserved bits:

  • On reads:

    • 0: interrupt not pending.

    • 1: interrupt pending.

  • On writes:

    • 0: no effect.

    • 1: clears the pending state of the interrupt.

Table 3.8. IRQ_CLR_STATUS register
BitsNameDescriptionAccessReset
[31:3]-ReservedRO, RAZ0
[2]NEXTThis interrupt is set by hardware during word-write operation whenever hardware is ready to accept the next word.RW0
[1]TIMEOUT

This interrupt is set by hardware when any row-write operation is finished by hardware as a result of software not clearing the NEXT interrupt within the specified time.

On reads:

0 = Interrupt is not pending.

1 = Interrupt is pending.

On writes:

0 = No effect.

1 = Clears the pending state of the interrupt.

RW0
[0]READY

This interrupt is set by hardware when any word-write, row-write, page-erase, or mass-erase operation finishes.

On reads:

0 = Interrupt is not pending.

1 = Interrupt is pending.

On writes:

0 = No effect.

1 = Clears the pending state of the interrupt.

RW0

IRQ_MASKED_STATUS register

Shows for each interrupt if it is pending and the cause of the interrupt line being asserted.

RO register at offset 0x1010.

  • On reads:

    • 0: interrupt is not causing IRQ line assertion.

    • 1: interrupt is cause of IRQ line assertion. Interrupt is pending and enabled.

Table 3.9. IRQ_MASKED_STATUS register
BitsNameDescriptionAccessReset
[31:3]-ReservedRO, RAZ0
[2]NEXT-RO0
[1]TIMEOUT-RO0
[0]READY-RO0

CTRL register

eFlash control register.

If FLSSAFESTATEREQn or FLSSHUTDOWNREQn is asserted, the eFlash controller rejects any write attempt to this register and responds with an APB ERROR response.

RW register at offset 0x0014.

Table 3.10. CTRL register
BitsNameDescriptionAccessReset
[31:5]-ReservedRO, RAZ0
[4]STOPStop any write or erase operation. High-voltage discharge is taken care of by eFlash Controller.RW0
[3]MASS_ERRASEErase all pages of eFlash.RW0
[2]ERASEErase one page of eFlash.RW0
[1]ROW_WRITEWrite one or more words (32 bit) to a row of eFlash (to sequential addresses) during one high-voltage period.RW0
[0]WRITEWrite one word (32 bit) of data to eFlash.RW0

STATUS register

Status or read or erase operation.

RO register at offset 0x1018.

Table 3.11. STATUS register
BitsNameDescriptionAccessReset
[31:2]-ReservedRO, RAZ0
[1]LOCK

Write/Erase lock. Lock conditions are FLSSAFESTATEREQn asserted or FLSSHUTDOWNREQn asserted.

0: Write and Erase operations can be executed by the eFlash controller.

1: The eFlash controller rejects any write or erase and responds with an APB ERROR response.

RO1
[0]BUSYeFlash Controller is executing any write or erase operation. Indicates that any eFlash bank is in HV state.RO0

CONFIG0 register

Configuration register.

RW register at offset 0x101C.

Table 3.12. CONFIG0 register
BitsNameDescriptionAccessReset
[31:26]-ReservedRO, RAZ0
[25:16]ER_CLK_COUNT

Erase clock configuration register.

Set the number of clock cells in 1ms period.

(ER_CLK_COUNT + 1) × Clock_period > 1ms

Minimum value is the nearest integer that results in a period > 1ms.

The clock source is always EXTCLK. The valid EXTCLK frequency range is 1kHz - 1MHz.

This register is not implemented if FLS_EXTCLKEN parameter set to 0.

RWFLS_ERCLKCOUNTRST parameter
[15:8]WR_CLK_COUNT

Write clock configuration register.

Set the number of clock cells in 1µs period.

If EXT_CLK_CONF is 0b00 or 0b01 then (WR_CLK_COUNT × HCLK-period) ≥ 1µs.

If EXT_CLK_CONF is 0b10 then (WR_CLK_COUNT × EXTCLK-period) ≥ 1µs.

RWFLS_WRCLKCOUNTRST parameter
[7:6]ETC_CLK_CONF

Write/erase timers source clock configuration.

If FLS_EXTCLKEN parameter is set to 0, then this field is tied to 0b00.

0b00 [Internal] External clock not used.

0b01 [Erase] External clock used for erase counters (>1ms). HCLK used for write counters.

0b10 [Write] External clock used for write and erase counters (>1µs).

0b11 [Reserved].

RW0b00
[5:0]RD_CLK_COUNT

Read clock configuration register.

0x0 Reserved.

0x1 1_cycle_read_mode. This value is allowed only if FLS_HALFCLKREAD parameter is set to 1.

Read from eFlash in 1 clock cycle over AHB interface. Read from eFlash in 2 clock cycles over APB interface.

0x2-03F normal_read_mode. eFlash read operation requires RD_CLK_COUNT number of HCLK cycles.

RWFLS_RDCLKCOUNTRST parameter

CONFIG1 register

Configuration register.

RW register at offset 0x1020.

Table 3.13. CONFIG1 register
BitsNameDescriptionAccessReset
[31:26]TNVHeFlash timing parameter. NVSTR hold time (µs).RWFLS_TNVH_RST parameter
[23:16]TPROG

eFlash timing parameter. Programming time (µs).

RWFLS_TPROG_RST parameter
[15:8]TPGS

eFlash timing parameter. NVSTR to program setup time (µs).

RWFLS_TPGS_RST parameter
[7:0]ETC_CLK_CONFeFlash timing parameter. PROG or ERASE to NVSTR setup time (µs).RWFLS_TNVS_RST parameter

CONFIG2 register

Configuration register.

RW register at offset 0x1024.

Table 3.14. CONFIG2 register
BitsNameDescriptionAccessReset
[31:24]TMEeFlash timing parameter. Mass erase time (ms).RWFLS_TME_RST parameter
[23:16]TERASE

eFlash timing parameter. Erase time (ms).

RWFLS_TERASE_RST parameter
[15:8]TRCV

eFlash timing parameter. Recovery time (µs).

RWFLS_TRCV_RST parameter
[7:0]TNVH1

eFlash timing parameter. NVSTR1 hold time (µs).

RWFLS_TNVH1_RST parameter

WADDR register

Write/Erase address register for the eFlash info page.

RW register at offset 0x1028.

Attempting to write an unmapped address into this register results in an APB ERROR response and the register value is not modified.

It is responsibility of software to ensure that the addressed word of eFlash is in erased state.

To erase a page of eFlash memory:

  1. Write the address of the page to erase to the WADDR register.

  2. Set the ERASE bit of CTRL register to start the operation.

Table 3.15. WADDR register
BitsDescriptionAccessReset
[31:30]

Bank select:

  • 0b01: Select bank 0 information page.

  • 0b10: Select bank 1 information page.

RW0
[29:11]Write as zero.RW0
[10:9]X address bits[1:0]RW0
[8:4]Y address bits[4:0]RW0
[1:0]Word select.RO0
[1:0]Reserved. Only word addressing is allowed. Bits[1:0] are tied to 0.RO0

WDATA register

Write data register.

RW register at offset 0x102C.

Table 3.16. WDATA register
BitsNameDescriptionAccessReset
[31:0]WDATA-RW0

EFUSE register

Each bit of this register corresponds to an emulated fuse value. EFUSE[0] = eFuse 0.

RO register at offset 0x1030.

Table 3.17. EFUSE register
BitsNameDescriptionAccessReset
[31:0]EFUSEEFUSE[0] is efuse 0.RO0

HWPARAMS0 register

Timeout and clock control register. The value of this register is defined by the system designer.

RO register at offset 0x1034.

Table 3.18. HWPARAMS0 register
BitsNameDescriptionAccessReset
[31:16]-ReservedRO, RAZ0
[15:8]TIMEOUTRow-write timeout parameterRO0x20
[7]DOUT_MASKIf set to 1, indicates additional gating inserted between controller and bus.RO, RAZ0
[6]EXTCLKENEnable EXTCLK inputRO0
[5]HALFCLKRDAllow setting RD_CLK_COUNT to 0RO0
[4:0]FLASHSIZEFLASHSIZE parameter = log2(eFlash size in bytes)RO0x11

HWPARAMS1 register

Clock count parameters. The value of this register is defined by the system designer.

RO register at offset 0x1038.

Table 3.19. HWPARAMS1 register
BitsNameDescriptionAccessReset
[31:26]-ReservedRO, RAZ0
[25:12]ERCLKCOUNTRSTReset value of ER_CLK_COUNT register.RO0
[11:4]WRCLKCOUNTRSTReset value of WR_CLK_COUNT register,RO0
[3:0]RDCLKCOUNTRSTReset value of RD_CLK_COUNT register.RO0x3F

HWPARAMS2 register

eFlash timing parameters. The value of this register is defined by the system designer.

RO register at offset 0x103C.

Table 3.20. HWPARAMS2 register
BitsNameDescriptionAccessReset
[31:24]TNVH_RSTeFlash timing parameter. NVSTR hold time (µs).RO0
[23:16]TPROG_RSTeFlash timing parameter. Programming time (µs).RO0
[15:8]TPGS_RSTeFlash timing parameter. NVSTR to program setup time (µs).RO0
[7:0]TNVS_RSTeFlash timing parameter. PROG/ERASE to NVSTR setup time (µs).RO0

HWPARAMS3 register

eFlash timing parameters for erase and hold. The value of this register is defined by the system designer.

RO register at offset 0x1040.

Table 3.21. HWPARAMS3 register
BitsNameDescriptionAccessReset
[31:24]TME_RSTeFlash timing parameter. Mass erase time (ms).RO0
[23:16]TERASE_RSTeFlash timing parameter. Erase time (ms).RO0
[15:8]TRCV_RSTeFlash timing parameter. Recovery time (µs).RO0
[7:0]TNVH1_RSTeFlash timing parameter. NVSTR1 hold time (µs).RO0

Product ID Register, PIDR4

eFlash parameters for address space.

RO register at offset 0x1FD0.

Table 3.22. PIDR4 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:4]SIZE8k address spaceRO0x1
[3:0]DES_2JEP 106 continuation codeRO0x4

Product ID Register, PIDR5

Reserved.

RO register at offset 0x1FD4.

Table 3.23. PIDR5 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]-ReservedRO, RAZ0

Product ID Register, PIDR6

Reserved.

RO register at offset 0x1FD8.

Table 3.24. PIDR6 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]-ReservedRO, RAZ0

Product ID Register, PIDR7

Reserved.

RO register at offset 0x1FDC.

Table 3.25. PIDR7 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]-ReservedRO, RAZ0

Product ID Register, PIDR0

eFlash part number.

RO register at offset 0x1FE0.

Table 3.26. PIDR0 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]PART_0Bits [7:0] of the part number.RO, RAZ0x30

Product ID Register, PIDR1

eFlash part number.

RO register at offset 0x1FE4.

Table 3.27. PIDR1 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:4]DES_0Bits [11:8] of the part number.RO, RAZ0xB
[3:0]PART_0Bits [11:8] of the part number.RO, RAZ0x8

Product ID Register, PIDR2

eFlash revision number.

RO register at offset 0x1FE8.

Table 3.28. PIDR2 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:4]REVISIONRevision number of the peripheral.RO, RAZ0
[3]JEDECAlways set. Indicates that a JEDEC assigned value is used.RO, RAZ0x1
[2:0]DES_1JEP106 identification code, bits[6:4]RO, RAZ0x3

Product ID Register, PIDR3

eFlash customer-modified number.

RO register at offset 0x1FEC.

Table 3.29. PIDR3 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:4]REVANDECO revisionRO, RAZ0
[3:0]CMODCustomer modified numberRO, RAZ0

Component ID Register, CIDR0

eFlash parameter register.

RO register at offset 0x1FF0.

Table 3.30. CIDR0 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]PRMBL_0-RO0x0D

Component ID Register, CIDR1

eFlash parameter register for IP component.

RO register at offset 0x1FF4.

Table 3.31. CIDR1 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:4]CLASSComponent classRO0xF
[3:0]PRMBL_1-RO0x0

Component ID Register, CIDR2

eFlash parameter register.

RO register at offset 0x1FF8.

Table 3.32. CIDR2 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]PRMBL_2-RO0x05

Component ID Register, CIDR3

eFlash parameter register.

RO register at offset 0x1FFC.

Table 3.33. CIDR3 register
BitsNameDescriptionAccessReset
[31:8]-ReservedRO, RAZ0
[7:0]PRMBL_3-RO0xB1

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