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1.1. Features of the CG092

The CG092 AHB Flash Cache is an instruction cache designed to be instantiated between the bus interconnect and the eFlash controller. The CG092 has the following characteristics:

  • Configurable cache size (minimum 256 bytes/way).

  • Four words per cacheline.

  • Supports 2-way set associative cache, or 1-way fully associative cache.

  • Configurable address bus size (based on flash memory size) so that tag memory size can be minimized.

  • SRAM power-control handshaking to an external power management unit.

  • Supports automatic and manual SRAM power up and power down (with simple handshaking).

    If valid data is in the powered-down cache because the cache is in a low-power state, the cache contents should not be invalidated on wake up. The software can therefore save energy by avoiding invaliding the cache RAMs on wake up.

  • Supports automatic or manual cache invalidate in the enabling sequence.

    This behavior can be overridden.

  • 32 bit AHB slave interface to the AHB master in the system processor.

  • 32 bit APB slave interface to the memory-mapped registers of the CG092.

  • 128-bit AHB master interface to the eFlash.


    An eFlash controller is not supplied with the CG092 component.

  • Interrupt request generated on SRAM power or manual invalidation errors.

  • Optional run-time support for prefetch to improve performance when executing a sequence of code that has not been read before.


    The prefetching performance impact is application dependent and might have a negative impact on eFlash power consumption.

  • Optional compile-time support configurable performance counters that measure cache hits and misses.

    Exported cache hit and cache miss status signals can be used by performance measurement logic implemented at SoC level.

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