The 128-bit AHB master interface of the CG092 is an AHB-Lite interface with the following limitations and extensions:
The HBURSTM port is tied to
0b000. The CG092 always makes SINGLE transfers.
Locked transfers are not supported. HMASTLOCKM port is tied to
HTRANSM is tied to LOW inside the cache thus it will not propagates transfers from AHB slave to AHB master interface unmodified even in bypass mode. SEQ transfers are translated to NONSEQ transfers while BUSY transfers are translated to IDLE transfers.
There is no power or speed gain in burst operations, so AHB bursts on are not supported on the AHB master interface:
From the time the CG092 is enabled, the direct connection between the AHB Slave and Master interface is closed. The CG092 drives HTRANSM to IDLE and makes only NONSEQ transaction if a bypass, linefill or prefetch transaction must be executed.
HSELM is continuously driven with
0b1and transactions received with HSELS
0b0on the AHB slave interface are not propagated to the AHB master interface. (HTRANSM remains in IDLE).
The CG092 is transparent if disabled. If therefore a master/interconnect driving the AHB slave interface cancels/terminates a burst, this will appear on the AHB master interface. The CG092 might change control signals on the AHB master interface during a waited transfer (terminating and starting a new address phase)