Cache becomes disabled/enabled on burst boundaries. If the CCR.EN is set/unset during a burst, the CG092 enables/disables itself only after the current burst is finished. The CG092 therefore starts/stops caching (cache lookup, making linefills, prefetching) after the current burst.
After CCR.EN is cleared, the CG092 can preform a prefetch transaction on the AHB master interface while the last AHB burst finishes on the Slave interface. In this case:
The CG092 waits with disabling until the prefetch transaction AHB data phase is finished.
No new linefill, prefetch is allowed to be executed from this point.
After the prefetch is finished, CG092 starts disabling.
Because the cache disables itself on burst boundaries, if a power error occurs the cache issues a power error interrupt but cannot disable itself immediately on detecting SRAM resource loss (RAMPWRACK=0). Invalid data might be returned on the AHB Slave port if a cache hit happens.
This limitation is valid only when the burst is on the bus with HSELS=1, otherwise the CG092 can switch state independently from the burst boundaries.
There are some restrictions on cache enable depending on cache state and the APOW and AINV signals. See Enabling the cache.