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1.3.4. Linefill

This section describes linefill limitations.

Debug Accesses

Debug accesses (indicated by HMASTERS = 1):

  • Are not cached.

  • Are not looked up in the cache.

  • Do not cause linefill or instruction prefetching.

These transactions are simply bypassed by the CG092.

Error Response

If the CG092 receives an error response (HRESPM = 1) for a read request, it will not update the internal linefill buffer and will not write the data into the SRAM.

If the read request was initiated by the AHB master the CG092 will propagate the received error response to the initiator, but if the read request was a result of prefetching the response is simply ignored.

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