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2.11.1. Functional description

The AHB5 to internal SRAM interface module enables on-chip synchronous RAM blocks to attach to an AHB5 interface. It performs read and write operations with zero wait states. The design supports 32-bit SRAM with byte writes.

Figure 2.15. AHB5 to internal SRAM interface module

If a read operation follows immediately after a write operation, the write address and write data are stored in an internal buffer. The stalled write transfer is carried out when the AHB5 interface is idle, or when a new write transfer arrives. This process occurs transparently and does not result in any wait states.

The module can store/read data to/from the memory both in little endian and byte- invariant and word invariant big endian formats. The used format can be configured using the endianness parameter.

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