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2.11.2. Port list

The following table shows the port list of the AHB5 to internal SRAM interface.

Table 2.21. Port list
BlockSignalDirectionDescription
SystemhclkInputClock
hresetnInputReset
AHB5 Slave Initiatorhaddr[ADDR_WIDTH-1:0]InputAddress, configurable width (ADDR_WIDTH)
 hsize[2:0]InputSize of the transfer
 htrans[1:0]InputTransfer type
 hwdata[31:0]InputWrite data
 hwriteInputTransfer direction indicator
 hrdata[31:0]OutputRead data
 hreadyoutOutputTransfer completion indicator
 hrespOutputTransfer response
 hselInputSlave select
 hreadyInputTransfer completion indicator
External Memory sram_addr[ADDR_WIDTH-1:0]OutputAddress, configurable width (ADDR_WIDTH)
sram_wdata[31:0]OutputWrite data
sram_rdata[31:0]InputRead Data
sram_wen[3:0]OutputWrite Enable
sram_csOutputChip Select
DFTdftramholdInputDFT bypass for RAM CS

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