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2.29.2. Port list

The following table shows the port list of the external asynchronous 8-bit SRAM.

Table 2.59. Port list
BlockSignalDirectionDescription
SystemclkInputClock
RAM interfaceaddr[ADDR_WIDTH-1:0]InputAddress, configurable width
dataio[15:0]BidirectionalData.
we_nInputWrite enable, active low.
oe_nInputOutput enable. Active low for read operation.
ce_nInputChip enable. Active low for both read and write operations.
lb_nInputLower byte enable, active low.
ub_nInputUpper byte enable, active low.