The AHB5 RAM wrapper model is a verification component and is not synthesizable RTL. The model enables easy switching between the following implementations of RAM, depending on the setting of the MEM_TYPE parameter:
Behavioral RAM model usign behaviorial SRAM with write disabled.
SRAM model with an AHB5 SRAM interface module, suitable for ASIC or FPGA flow.
16-bit SRAM model with an AHB5 external SRAM interface.
8-bit SRAM model with an AHB5 external SRAM interface.
The following figure shows the ROM wrapper model.