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1.2. Product revisions

This section describes the differences in functionality between product revisions of the CoreLink SIE-200 System IP for Embedded:


First release.


Second release. Functional improvement to AMBA® AHB5 downsizer.


Third release. Added the following:

  • AHB5 example slave.

  • AHB5 GPIO.

  • AHB5 timeout monitor.

  • AHB5 to external SRAM interface.

  • AHB5 to ROM interface.

  • Cortex-M3/Cortex-M4 AHB5 adapter.

  • Behavioral SRAM model with an AHB5 interface.

  • External asynchronous 8-bit SRAM model.

  • External asynchronous 16-bit SRAM model.

  • FPGA SRAM synthesizable model.

  • RAM wrapper model.

  • ROM behavioral model.

  • ROM wrapper model.

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