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Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Issue A
ChangeLocationAffects
First release--

Table A.2. Differences between issue A and issue B
ChangesLocationAffects
Updates, corrections, and improvements for Beta releaseThroughout document.r0p0

Table A.3. Differences between issue B and issue C
ChangesLocationAffects
Updates, corrections, and improvements for Beta updateThroughout document.r0p0

Table A.4. Differences between issue C and issue D
ChangesLocationAffects
Updates, corrections, and improvements for LAC releaseThroughout document.r1p0

Table A.5. Differences between issue D and issue E
ChangesLocationAffects
Updates, corrections, and improvements for EAC releaseThroughout document.r2p0
Added modules and models for EAC release

AHB5 example slave.

AHB5 GPIO.

AHB5 timeout monitor.

AHB5 to external SRAM interface.

AHB5 to ROM interface.

Cortex-M3/Cortex-M4 AHB5 adapter.

Behavioral SRAM model with an AHB5 interface.

External asynchronous 8-bit SRAM model.

External asynchronous 16-bit SRAM model.

FPGA SRAM synthesizable model.

RAM wrapper model.

ROM behavioral model.

ROM wrapper model.

Other mentions of these modules and models throughout document.

r2p0

Table A.6. Differences between issue E and issue F
ChangesLocationAffects
Added modules and models for EAC2 release

Comparison between bridges and their low-latency versions.

AHB5 to AHB5 low-latency sync-down bridge.

AHB5 to AHB5 low-latency sync-up bridge.

AHB5 to APB4 low-latency sync-down bridge.

Other mentions of these modules and models throughout document.

r3p0
Modified TrustZone AHB5 memory protection controller. Minimum number of blocks changed from 64 to 2.

AHB5 TrustZone memory protection controller.

Other mentions of these modules and models throughout document.

r3p0

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