The AHB5 Access Control Gate (ACG) IP component can be placed on a clock or power domain boundary to pass or block AHB5 transfers whenever the receiving side of the transaction cannot accept the transfer, or is explicitly asked not to do so. The transfer is latched internally and the module generates automatic responses when necessary.
The ACG serves as the boundary element of the clock or power domains:
When both domains are on, the ACG is invisible on the bus and AHB5 transfers pass through it without any delay.
When either the clock or the power domain is down, as indicated by the Q-channel states, the ACG generates a waited transfer response, so that an incoming transfer is delayed.
It informs the power and clock controllers that power and clock are required, so a wake-up sequence must be initiated. The ACG also denies quiescence requests from any Q-channels when there are ongoing transfers through the ACG.
Optionally, the ACG can respond with a standard AHB5 Error response when the transfers cannot pass through it due to quiescent Q-channel states. The wake up request is not made to the dormant Q-channel when using this mode of operation.
Table 2.26 shows the behavior of the ACG.
|EXT GATE ACK||CFG GATE RESP||Any clock or power Q-channel in Q_STOP||Expected ACG/bridge behavior|
|0||X||0||Transfers pass through. Deny Q-channel requests during transfers. Accept Q-channel requests when there is no incoming transfer.|
|X||0||1||Hold transfers and show hreadyout_s = 0. Wake up Q-channels when transfer arrives.|
|X||1||1||Generate Error response for incoming transfers. Do not wake up Q-channels.|
|1||0||0||Hold transfers and show hreadyout_s = 0. Deny Q-channel requests during transfers. Accept Q-channel requests when there is no incoming transfer.|
|1||1||0||Generate Error response for incoming transfers. Accept Q-channel requests even during sending error responses.|
Figure 2.19 shows the AHB5 access control gate: