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2.20.1. Functional description

The AHB5 to AHB5 sync-up bridge synchronizes AHB5 interfaces where the upstream side is slower than the downstream side and the clocks are synchronous, in phase, and have a 1:N frequency ratio. It can also be placed on power and clock domain boundaries due to its Q-channel handling capabilities.

A parameter defines whether burst transfers are converted into single transfers on the downstream side, or BUSY sequences are inserted while waiting for the new upstream data to arrive. Otherwise the bridge inserts IDLE transfers to the attached slave. If burst is supported and the bridge receives an error response on the downstream side during the sequential beats of the burst, it cancels the remaining transfers in the burst. The upstream side rejects the remainder of the burst by providing error responses while the downstream side is kept in IDLE state.

Note

An error response on the upstream side only appears as an error interrupt if the respective (bufferable, non-exclusive) write transfer is buffered.

A single write can be buffered in the 1-deep write buffer of the upstream side. When a non-exclusive write transfer is marked as bufferable, and there is a transfer already pending in the latch, the write buffer can store the incoming write and respond back to the slave with a ready response. Due to the nature of buffering, it is possible that an error response only occurs after the data phase of the write transfer, in which case an active high level interrupt is generated on the slow clock as an error signal towards the initiator of the transfer.

When master lock sequences are detected, the downstream side automatically inserts IDLE transfers between two locked sequences as recommended by the AHB5 specification.

The module denies Q-channel requests when there is a pending transfer or a pending error interrupt from the write buffer. Note that the same power-down procedure has to be followed regardless of the write buffer. The system has to guarantee that power-down is not initiated before the last transfer is properly acknowledged by hreadyout_s. This condition guarantees that the bridge completes the transfer before the power is removed.

The bridge has two clock inputs:

  • hclk_m on the downstream side.

  • hclk_s on the upstream side.

The two clocks are semi-synchronous, that is, hclk_m is an integer multiple of hclk_s.

The bridge consists of three major blocks:

  • An AHB slave on the upstream side.

  • An AHB master on the downstream side.

  • The handler for all Q-channel interfaces:

    • Logic for response handling.

The following figure shows the AHB5 to AHB5 sync-up bridge module.

Figure 2.26. AHB5 to AHB5 sync-up bridge

Figure 2.26. AHB5 to AHB5 sync-up bridge