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2.20.2. Port list

The following table shows the port list of the AHB5 to AHB5 sync-up bridge.

Table 2.39. Port list
BlockSIGNALDIRECTIONDESCRIPTION
Systemhclk_sInputClock for the upstream side
hresetn_sInputReset for the upstream side
hclk_mInputClock for the downstream side (synchronous with hclk_s, frequency is N time hclk_s)
hresetn_mInputReset for the downstream side
AHB5 Slavehsel_sInputSlave select
hnonsec_sInputNon-secure transfer indicator
haddr_s[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans_s[1:0]InputTransfer type
hsize_s[2:0]InputSize of the transfer
hwrite_sInputTransfer direction indicator
hready_sInputTransfer completion indicator
hprot_s[6:0]InputProtection control
hburst_s[2:0]InputBurst type
hmastlock_sInputLocked sequence indicator
hwdata_s[DATA_WIDTH-1:0]InputWrite data, configurable width
hexcl_sInputExclusive Transfer indicator
hmaster_s[MASTER_WIDTH-1:0]InputMaster identifier
hrdata_s[DATA_WIDTH-1:0]OutputRead data, configurable width
hreadyout_sOutputTransfer completion indicator
hresp_sOutputTransfer response
hexokay_sOutputExclusive okay
hruser_s[USER_WIDTH-1:0]OutputRead channel user signals, configurable width
hauser_s[USER_WIDTH-1:0]InputAddress channel user signals, configurable width
hwuser_s[USER_WIDTH-1:0]InputWrite channel user signals, configurable width
AHB5 Masterhnonsec_mOutputNon-secure transfer indicator
haddr_m[ADDR_WIDTH-1:0]OutputAddress, configurable width
htrans_m[1:0]OutputTransfer type
hsize_m[2:0]OutputSize of the transfer
hwrite_mOutputTransfer direction indicator
hready_mInputTransfer completion indicator
hprot_m[6:0]OutputProtection control
hburst_m[2:0]OutputBurst type
hmastlock_mOutputLocked sequence indicator
hwdata_m[DATA_WIDTH-1:0]OutputWrite data, configurable width
hexcl_mOutputExclusive Transfer indicator
hmaster_m[MASTER_WIDTH-1:0]OutputMaster identifier
hrdata_m[DATA_WIDTH-1:0]InputRead data, configurable width
hresp_mInputTransfer response
hexokay_mInputExclusive okay
hruser_m[USER_WIDTH-1:0]InputRead channel user signals, configurable width
hauser_m[USER_WIDTH-1:0]OutputAddress channel user signals, configurable width
hwuser_m[USER_WIDTH-1:0]OutputWrite channel user signals, configurable width
Q-channel Upstream sidehclk_qactive_sOutput

Clock active indication to clock controller

hclk_qreqn_sInput

Clock Q Request from clock controller (active low)

hclk_qacceptn_sOutput

Clock Q Accept to clock controller

(active low)

hclk_qdeny_sOutput

Clock Q Deny to clock controller

Q-channel Downstream sidehclk_qactive_mOutput

Clock active indication to clock controller

hclk_qreqn_mInput

Clock Q Request from clock controller (active low)

hclk_qacceptn_mOutput

Clock Q Accept to clock controller (active low)

hclk_qdeny_mOutput

Clock Q Deny to clock controller

Power Q-channel (on downstream side)pwr_qactive_sOutput

Power active indication to power controller

pwr_qreqn_sInput

Power Q Request from power controller (active low)

pwr_qacceptn_sOutput

Power Q Accept to power controller (active low)

pwr_qdeny_sOutput

Power Q Deny to power controller

Miscahb5_sync_up_irqOutput

Bufferable write error interrupt,

active high-level

ahb5_sync_up_irq_clearInputBufferable write error interrupt clear
ext_gate_reqInputExternal gating request
ext_gate_ackOutputExternal gating acknowledge
ext_gate_respInput

Response type selector when ACG is off:

0: Waited transfer

1: Error response