You copied the Doc URL to your clipboard.

2.27.2. Port list

The AHB5 TrustZone memory protection controller gates transactions to the AHB5 master interface when a security violation occurs. It can be instantiated in the system in connection to any non-security aware AHB5 memory. The security checking is done based on block/page level which is configured externally by the security controller through an APB interface.

The AHB5 TrustZone memory protection controller provides a full AHB5 Slave interface towards the upstream side and an AHB5 Master interface towards the downstream side of the AHB5 bus, similar to any other bridge-like component. It also provides an APB slave interface for the configuration registers which can be set by the security controller in the system with secure accesses (PPROT[1]==0) only. Identification registers can be read by any type of access. A dedicated interrupt signal is asserted whenever a security violation is detected. The interrupt must be enabled by both the register bank, and by mpc_irq_enable input to enable the assertion of the interrupt signal. The interrupt is cleared by writing to the appropriate register.

The following table shows the port list of the AHB5 TrustZone memory protection controller.

Table 2.54. Port list
SystemhclkInputClock AHB5 and APB side
hresetnInputReset for AHB5 and APB domain
AHB5 Slave Interfacehsel_sInputSlave select
hnonsec_sInputNon-secure transfer indicator
haddr_s[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans_s[1:0]InputTransfer type
hsize_s[2:0]InputSize of the transfer
hwrite_sInputTransfer direction indicator
hready_sInputHREADY feedback from all slaves
hprot_s[6:0]InputProtection control
hburst_s[2:0]InputBurst type
hmastlock_sInputLocked sequence indicator
hwdata_s[DATA_WIDTH-1:0]InputWrite data, configurable width.
hexcl_sInputExclusive Transfer indicator.
hmaster_s[MASTER_WIDTH-1:0]InputMaster identifier, configurable width
hrdata_s[DATA_WIDTH-1:0]OutputRead data, configurable width.
hreadyout_sOutputTransfer completion indicator
hresp_sOutputTransfer response
hexokay_sOutputExclusive okay
hruser_s[USER_WIDTH-1:0]OutputRead channel user signals, configurable width
hauser_s[USER_WIDTH-1:0]InputAddress channel user signals, configurable width
hwuser_s[USER_WIDTH-1:0]InputWrite channel user signals, configurable width
AHB5 Master Interfacehsel_mOutputSlave select pass-through
hnonsec_mOutputNon-secure transfer indicator
haddr_m[ADDR_WIDTH-1:0]OutputAddress, configurable width
htrans_m[1:0]OutputTransfer type
hsize_m[2:0]OutputSize of the transfer
hwrite_mOutputTransfer direction indicator
hready_mOutputHREADY feedback to all slaves.
hprot_m[6:0]OutputProtection control
hburst_m[2:0]OutputBurst type
hmastlock_mOutputLocked sequence indicator
hwdata_m[DATA_WIDTH-1:0]OutputWrite data, configurable width
hexcl_mOutputExclusive Transfer indicator.
hmaster_m[MASTER_WIDTH-1:0]OutputMaster identifier
hrdata_m[DATA_WIDTH-1:0]InputRead data, configurable width
hreadyout_mInputTransfer completion indicator
hresp_mInputTransfer response
hexokay_mInputExclusive okay
hruser_m[USER_WIDTH-1:0]InputRead channel user signals, configurable width
hauser_m[USER_WIDTH-1:0]OutputAddress channel user signals, configurable width
APB InterfacepselInputSlave select
paddr[11:0]InputAddress allowing 4 KB space
pstrb[3:0]InputWrite strobe
pwriteInputTransfer direction indicator
pprot[2:0]InputProtection control
pwdata[31:0]InputWrite data
prdata[31:0]OutputRead data
preadyOutputTransfer completion indicator
pslverrOutputTransfer response
Miscellaneousmpc_irqOutputSecurity violation interrupt

Enable security violation interrupt generation:

0: Security interrupt generation logic turned off

1: Security interrupt generation logic turned on


Selection of default content at initialization for all blocks

0: Secure

1: Non-Secure