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2.31.2. Port list

The following table shows the port list of the behavioral SRAM model with an AHB5 interface.

Table 2.64. Port list
SystemhclkInputClock AHB side
hresetnInputReset for hclk domain
AHB5 Slave interfacehselInputSlave select
haddr[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans[1:0]InputTransfer type
hsize[2:0]InputSize of the transfer
hwriteInputTransfer direction indicator
hreadyInputhready feedback from all slaves
hwdata[31:0]InputWrite data
hrdata[31:0]OutputRead data
hreadyoutOutputTransfer completion indicator
hrespOutputTransfer response