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2.34.1. Functional description

The FPGA SRAM synthesizable model is a model for SRAM that behaves like simple synchronous RAM in ASIC or FPGA. This memory does not have an AHB5 interface and the AHB5 to SRAM interface is required to connect the memory to AHB5. The model demonstrates the use of the AHB5 to SRAM interface and is suitable for FPGA synthesis.

The following figure shows the model.

Figure 2.45. FPGA SRAM synthesizable model

Figure 2.45. FPGA SRAM synthesizable model