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2.34.2. Port list

The following table shows the port list of the FPGA SRAM synthesizable model.

Table 2.67. Port list
BlockSignalDirectionDescription
SystemclkInputClock
RAM interfaceaddr[ADDR_WIDTH-1:2]InputAddress, configurable width.
wdata[31:0]InputWrite data
wren[31:0]InputWrite enable
csInputChip select
rdata[31:0]OutputRead data