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2.36.2. Port list

The following table shows the port list of the ROM behavioral model.

Table 2.70. Port list
BlockSignalDirectionDescription
SystemclkInputClock for wait state modeling
rst_nInputReset for wait state modeling
ROM interfacehaddr[ADDR_WIDTH_TOP-1:0]InputAddress, configurable width.
rdata[DATA_WIDTH-1:0]OutputRead data,configurable width

Note

ADDR_WIDTH_TOP = ADDR_WIDTH - X where X depends on DATA_WIDTH:

  • DATA_WIDTH = 32: X = 2.

  • DATA_WIDTH = 16: X =1.