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1.2. Product revisions

This section describes the differences in functionality between product revisions of the CoreLink SIE-200 System IP for Embedded:

r0p0

First release.

r1p0

Second release. Functional improvement to AMBA® AHB5 downsizer.

r2p0

Third release. Added the following:

  • AHB5 example slave.

  • AHB5 GPIO.

  • AHB5 timeout monitor.

  • AHB5 to external SRAM interface.

  • AHB5 to ROM interface.

  • Cortex-M3/Cortex-M4 AHB5 adapter.

  • Behavioral SRAM model with an AHB5 interface.

  • External asynchronous 8-bit SRAM model.

  • External asynchronous 16-bit SRAM model.

  • FPGA SRAM synthesizable model.

  • RAM wrapper model.

  • ROM behavioral model.

  • ROM wrapper model.

r3p0

Fourth release. Added the following:

  • ABHB5 to AHB5 low-latency sync-down bridge.

  • AHB5 to AHB5 low-latency sync-up bridge.

  • ABH5 to APB4 low-latency sync-down bridge.

Note

The low-latency bridges in release r3p0 are similar in function to their non-low-latency equivalents. They are options for designs that do not require Q-channel support for power management.

This option enables optimization for reduced latency in these three bridges.

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