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2.14.2. Port list

The AHB5 access control gate provides:

  • One upstream AHB5 interface and one downstream AHB5 interface.

  • Three Q-channel interfaces.

  • Sideband signals for configuration and the external blocking feature.

The following table shows the port list of the AHB5 access control gate.

Table 2.27. AHB5 access control gate port list
Systemhclk_sInputClock for the downstream side
hresetn_sInputReset for the downstream side
hclk_mInputClock for the upstream side (same phase and frequency as hclk_s)
hresetn_mInputReset for the upstream side
AHB5 Slavehsel_sInputSlave select
hnonsec_sInputNon-secure transfer indicator
haddr_s[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans_s[1:0]InputTransfer type
hsize_s[2:0]InputSize of the transfer
hwrite_sInputTransfer direction indicator
hready_sInputTransfer completion indicator
hprot_s[6:0]InputProtection control
hburst_s[2:0]InputBurst type
hmastlock_sInputLocked sequence indicator
hwdata_s[DATA_WIDTH-1:0]InputWrite data, configurable width
hexcl_sInputExclusive Transfer indicator
hmaster_s[MASTER_WIDTH-1:0]InputMaster identifier
hrdata_s[DATA_WIDTH-1:0]OutputRead data, configurable width
hreadyout_sOutputTransfer completion indicator
hresp_sOutputTransfer response
hexokay_sOutputExclusive okay
hruser_s[USER_WIDTH-1:0]OutputRead channel user signals, configurable width
hauser_s[USER_WIDTH-1:0]InputAddress channel user signals, configurable width
hwuser_s[USER_WIDTH-1:0]InputWrite channel user signals, configurable width
AHB5 Masterhsel_mOutputSlave select pass-through
hnonsec_mOutputNon-secure transfer indicator
haddr_m[ADDR_WIDTH-1:0]OutputAddress, configurable width
htrans_m[1:0]OutputTransfer type
hsize_m[2:0]OutputSize of the transfer
hwrite_mOutputTransfer direction indicator
hready_mOutputHREADY feedback to all slaves.
hprot_m[6:0]OutputProtection control
hburst_m[2:0]OutputBurst type
hmastlock_mOutputLocked sequence indicator
hwdata_m[DATA_WIDTH-1:0]OutputWrite data, configurable width
hexcl_mOutputExclusive Transfer indicator
hmaster_m[MASTER_WIDTH-1:0]OutputMaster identifier
hrdata_m[DATA_WIDTH-1:0]InputRead data, configurable width
hreadyout_mInputTransfer completion indicator
hresp_mInputTransfer response
hexokay_mInputExclusive okay
hruser_m[USER_WIDTH-1:0]InputRead channel user signals, configurable width
hauser_m[USER_WIDTH-1:0]OutputAddress channel user signals, configurable width
hwuser_m[USER_WIDTH-1:0]OutputWrite channel user signals, configurable width
Q-channel Upstream sidehclk_qactive_sOutputClock active indication to clock controller
hclk_qreqn_sInputClock Q Request from clock controller (active low)
hclk_qacceptn_sOutputClock Q Accept to clock controller (active low)
hclk_qdeny_sOutputClock Q Deny to clock controller
Q-channel Downstream sidehclk_qactive_mOutputClock active indication to clock controller
hclk_qreqn_mInputClock Q Request from clock controller (active low)
hclk_qacceptn_mOutputClock Q Accept to clock controller (active low)
hclk_qdeny_mOutputClock Q Deny to clock controller
Power Q-channel (on downstream side)pwr_qactive_sOutputPower active indication to power controller
pwr_qreqn_sInputPower Q Request from power controller (active low)
pwr_qacceptn_sOutputPower Q Accept to power controller (active low)
pwr_qdeny_sOutputPower Q Deny to power controller
Miscellaneousext_gate_reqInputExternal gating request

External gating acknowledge


Response type when the ACG is blocking the incoming transfers:

0: Waited transfer

1: Error response

See ARM® CoreLink™ SIE-200 System IP for Embedded Configuration and Integration Manual for more information on the use of ext_gate_req, ext_gate_ack, and cfg_gate_resp.

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