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2.16.2. Port list

The AHB5 to AHB5 and APB4 asynchronous bridge provides:

  • One upstream interface and one downstream interface.

  • A downstream APB interface.

  • Three Q-channel interfaces.

The following table shows the port list of the AHB5 to AHB5 and APB4 asynchronous bridge.

Table 2.31. AHB5 to AHB5 and APB4 asynchronous bridge port list
BlockSIGNALDIRECTIONDESCRIPTION
Systemhclk_sInputClock for the downstream side
hresetn_sInputReset for the downstream side
hclk_mInputClock for the upstream side
hresetn_mInputReset for the upstream side
AHB5 Slavehsel_ahb_sInputSlave select for AHB5 interface
hsel_apb_sInputSlave select for APB interface
hnonsec_sInputNon-secure transfer indicator
haddr_s[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans_s[1:0]InputTransfer type
hsize_s[2:0]InputSize of the transfer
hwrite_sInputTransfer direction indicator
hready_sInputTransfer completion indicator
hprot_s[6:0]InputProtection control
hburst_s[2:0]InputBurst type
hmastlock_sInputLocked sequence indicator
hwdata_s[DATA_WIDTH-1:0]InputWrite data, configurable width
hexcl_sInputExclusive Transfer indicator.
hmaster_s[MASTER_WIDTH-1:0]InputMaster identifier.
hrdata_s[DATA_WIDTH-1:0]OutputRead data, configurable width
hreadyout_sOutputTransfer completion indicator
hresp_sOutputTransfer response
hexokay_sOutputExclusive okay
hruser_s[USER_WIDTH-1:0]OutputRead channel user signals, configurable width
hauser_s[USER_WIDTH-1:0]InputAddress channel user signals, configurable width
hwuser_s[USER_WIDTH-1:0]InputWrite channel user signals, configurable width
AHB5 Masterhsel_mOutputSlave select pass-through
hnonsec_mOutputNon-secure transfer indicator
haddr_m[ADDR_WIDTH-1:0]OutputAddress, configurable width
htrans_m[1:0]OutputTransfer type
hsize_m[2:0]OutputSize of the transfer
hwrite_mOutputTransfer direction indicator
hready_mOutputHREADY feedback to all slaves
hprot_m[6:0]OutputProtection control
hburst_m[2:0]OutputBurst type
hmastlock_mOutputLocked sequence indicator
hwdata_m[DATA_WIDTH-1:0]OutputWrite data, configurable width
hexcl_mOutputExclusive Transfer indicator.
hmaster_m[MASTER_WIDTH-1:0]OutputMaster identifier
hrdata_m[DATA_WIDTH-1:0]InputRead data, configurable width
hreadyout_mInputTransfer completion indicator
hresp_mInputTransfer response
hexokay_mInputExclusive okay
hruser_m[USER_WIDTH-1:0]InputRead channel user signals, configurable width
hauser_m[USER_WIDTH-1:0]OutputAddress channel user signals, configurable width
hwuser_m[USER_WIDTH-1:0]OutputWrite channel user signals, configurable width
APB4 Masterpaddr_m[ADDR_WIDTH-1:0]OutputAddress
pprot_m[2:0]OutputProtection control
psel_mOutputSlave select
penable_mOutputEnable
pwrite_mOutputTransfer direction indicator
pwdata_m[31:0]OutputWrite data
pstrb_m[3:0]OutputWrite strobe
pready_mInputReady
prdata_m[31:0]InputRead data
pslverr_mInputTransfer failure
pmaster_m[MASTER_WIDTH-1:0]OutputMaster identifier, configurable width (MASTER_WIDTH)
Q-channel Upstream sidehclk_qactive_sOutputClock active indication to clock controller.
hclk_qreqn_sInputClock Q Request from clock controller (active low)
hclk_qacceptn_sOutputClock Q Accept to clock controller (active low)
hclk_qdeny_sOutputClock Q Deny to clock controller
Q-channel Downstream sidehclk_qactive_mOutputClock active indication to clock controller.
hclk_qreqn_mInputClock Q Request from clock controller (active low)
hclk_qacceptn_mOutputClock Q Accept to clock controller (active low)
hclk_qdeny_mOutputClock Q Deny to clock controller
Power Q-channel (on downstream side)pwr_qactive_sOutputPower active indication to power controller.
pwr_qreqn_sInputPower Q Request from power controller (active low).
pwr_qacceptn_sOutputPower Q Accept to power controller (active low).
pwr_qdeny_sOutputPower Q Deny to power controller.
Miscellaneoushactive_mOutputAHB5 interface active
pactive_mOutputAPB4 interface active
ext_gate_reqInputExternal gating request
ext_gate_ackOutput

External gating acknowledge

cfg_gate_respInput

Response type when the Access Control Gate (ACG) is blocking the incoming transfers:

0: Waited transfer

1: Error response


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