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2.19.2. Port list

The following table shows the port list of the AHB5 to AHB5 synchronous bridge.

Table 2.37. AHB5 to AHB5 synchronous bridge port list
BlockSIGNALDIRECTIONDESCRIPTION
SystemhclkInputClock for the downstream side
hresetnInputReset for the downstream side
AHB5 Slavehsel_sInputSlave select
hnonsec_sInputNon-secure transfer indicator
haddr_s[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans_s[1:0]InputTransfer type
hsize_s[2:0]InputSize of the transfer
hwrite_sInputTransfer direction indicator
hready_sInputTransfer completion indicator
hprot_s[6:0]InputProtection control
hburst_s[2:0]InputBurst type
hmastlock_sInputLocked sequence indicator
hwdata_s[DATA_WIDTH-1:0]InputWrite data, configurable width
hexcl_sInputExclusive Transfer indicator.
hmaster_s[MASTER_WIDTH-1:0]InputMaster identifier.
hrdata_s[DATA_WIDTH-1:0]OutputRead data, configurable width
hreadyout_sOutputTransfer completion indicator
hresp_sOutputTransfer response
hexokay_sOutputExclusive okay
hruser_s[USER_WIDTH-1:0]OutputRead channel user signals, configurable width
hauser_s[USER_WIDTH-1:0]InputAddress channel user signals, configurable width
hwuser_s[USER_WIDTH-1:0]InputWrite channel user signals, configurable width
AHB5 Masterhnonsec_mOutputNon-secure transfer indicator
haddr_m[ADDR_WIDTH-1:0]OutputAddress, configurable width
htrans_m[1:0]OutputTransfer type
hsize_m[2:0]OutputSize of the transfer
hwrite_mOutputTransfer direction indicator
hready_mInputTransfer completion indicator
hprot_m[6:0]OutputProtection control
hburst_m[2:0]OutputBurst type
hmastlock_mOutputLocked sequence indicator
hwdata_m[DATA_WIDTH-1:0]OutputWrite data, configurable width
hexcl_mOutputExclusive Transfer indicator
hmaster_m[MASTER_WIDTH-1:0]OutputMaster identifier
hrdata_m[DATA_WIDTH-1:0]InputRead data, configurable width
hresp_mInputTransfer response
hexokay_mInputExclusive okay
hruser_m[USER_WIDTH-1:0]InputRead channel user signals, configurable width
hauser_m[USER_WIDTH-1:0]OutputAddress channel user signals, configurable width
hwuser_m[USER_WIDTH-1:0]OutputWrite channel user signals, configurable width
Miscellaneousext_gate_reqInputExternal gating request
ext_gate_ackOutput

External gating acknowledge

cfg_gate_respInput

Response type when the Access Control Gate (ACG) is blocking the incoming transfers:

0: Waited transfer

1: Error response


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