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2.22.2. Port list

The AHB5 to APB4 asynchronous bridge has the following interfaces:

  • AHB5 Slave Initiator interface to connect to the AHB5 Bus.

  • APB4 Master Interface to connect to the peripheral device.

  • AHB5 Q-channel clock control.

  • AHB5 Q-channel power control.

  • APB4 Q-channel clock control.

The following table shows the port list of the AHB5 to APB4 asynchronous bridge.

Table 2.43. AHB5 to APB4 asynchronous bridge port list
SystemhclkInputAHB5 clock
hresetnInputAHB5 reset
pclkInputAPB4 clock
presetnInputAPB4 reset
apb_activeOutputAPB bus is active, for clock gating
AHB5 Slave InitiatorhselInputSlave select
haddr[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans[1:0]InputTransfer type
hsize[2:0]InputSize of the transfer
hwriteInputTransfer direction indicator
hreadyInputTransfer completion indicator
hprot[6:0]InputProtection control
hwdata[DATA_WIDTH-1:0]InputWrite data, configurable width
hmaster[MASTER_WIDTH-1:0]InputMaster identifier
hrdata[DATA_WIDTH-1:0]OutputRead data, configurable width
hreadyoutOutputTransfer completion indicator
hrespOutputTransfer response
hnonsecInputNon-secure Transfer Indicator
APB4 Masterpmaster[MASTER_WIDTH-1:0]OutputMaster identifier
paddr[ADDR_WIDTH-1:0]OutputAddress, configurable width
pprot[2:0]OutputProtection control
pwriteOutputTransfer direction indicator
pselOutputSlave select
pstrb[3:0]OutputWrite strobe
pwdata[31:0]OutputWrite data
prdata[31:0]InputRead data
pslverrInputTransfer failure
AHB5 clock control Q-channelhclk_qactive_sOutputClock active indication to clock controller
hclk_qreqn_sInputClock Q Request from clock controller (active low)
hclk_qacceptn_sOutputClock Q Accept to clock controller (active low)
hclk_qdeny_sOutputClock Q Deny to clock controller
AHB5 power control Q-channelpwr_qactive_sOutputPower active indication to power controller
pwr_qreqn_sInputPower Q Request from power controller (active low)
pwr_qacceptn_sOutputPower Q Accept to power controller (active low)
pwr_qdeny_sOutputPower Q Deny to power controller
APB4 clock control Q-channelpclk_qactive_mOutputClock active indication to clock controller
pclk_qreqn_mInputClock Q Request from clock controller (active low)
pclk_qacceptn_mOutputClock Q Accept to clock controller (active low)
pclk_qdeny_mOutputClock Q Deny to clock controller
Miscellaneousext_gate_reqInputExternal gating request

External gating acknowledge.


Response type when the Access Control Gate (ACG) is blocking the incoming transfers:

0: Waited transfer

1: Error response

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