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2.23.2. Port list

The AHB5 to APB4 sync-down bridge has the following interfaces:

  • AHB5 Slave Initiator interface to connect to the AHB5 Bus.

  • APB4 Master Interface to connect to the periphery device.

  • Q-channel for AHB5 side clock control.

  • Q-channel for APB4 side clock control.

  • Q-channel for power control.

The following table shows the port list of the AHB5 to APB4 sync-down bridge.

Table 2.45. AHB5 to APB4 sync-down bridge port list
BlockSIGNALDIRECTIONDESCRIPTION
SystemhclkInputAHB5 Clock
hresetnInputAHB5 Reset
pclkInputAPB side clock (balanced synchronous to AHB5 Clock)
presetnInputAPB Reset
apb_activeOutputAPB bus is active, for clock gating
AHB5 Slave InitiatorhselInputSlave select
hnonsecInputNon-secure transfer indicator
haddr[ADDR_WIDTH-1:0]InputAddress, configurable width
htrans[1:0]InputTransfer type
hsize[2:0]InputSize of the transfer
hwriteInputTransfer direction indicator
hreadyInputTransfer completion indicator
hprot[3:0]InputProtection control
hprot[6:4]Input

Protection control extension

(AHB5 only)

hwdata[31:0]InputWrite data, configurable width (DATA_WIDTH)
hmaster[MASTER_WIDTH-1:0]InputMaster identifier (MASTER_WIDTH)
hrdata[31:0]OutputRead data, configurable width
hreadyoutOutputDevice ready
hrespOutputTransfer response
APB4 Masterpmaster[MASTER_WIDTH-1:0]OutputMaster identifier (MASTER_WIDTH)
paddr[ADDR_WIDTH-1:0]OutputAddress, configurable width
pprot[2:0]OutputProtection control
pwriteOutputTransfer direction indicator
pselOutputSlave select
pstrb[3:0]OutputWrite strobe
penableOutputEnable
pwdata[31:0]OutputWrite data
prdata[31:0]InputRead data
preadyInputReady
pslverrInputTransfer failure
AHB5 clock control Q-channelhclk_qactive_sOutputClock active indication to clock controller
hclk_qreqn_sInputClock Q Request from clock controller (active low)
hclk_qacceptn_sOutputClock Q Accept to clock controller (active low)
hclk_qdeny_sOutputClock Q Deny to clock controller
AHB5 power control Q-channelpwr_qactive_sOutputPower active indication to power controller
pwr_qreqn_sInputPower Q Request from power controller (active low)
pwr_qacceptn_sOutputPower Q Accept to power controller (active low)
pwr_qdeny_sOutputPower Q Deny to power controller
APB4 clock control Q-channelpclk_qactive_mOutputClock active indication to clock controller
pclk_qreqn_mInputClock Q Request from clock controller (active low)
pclk_qacceptn_mOutputClock Q Accept to clock controller (active low)
pclk_qdeny_mOutputClock Q Deny to clock controller
Miscellaneousext_gate_reqInputExternal gating request
ext_gate_ackOutput

External gating acknowledge.

cfg_gate_respInput

Response type when the Access Control Gate (ACG) is blocking the incoming transfers:

0: Waited transfer

1: Error response


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