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3.3. AHB5 TrustZone memory protection controller

APB accesses are internally aligned to word boundaries, so PADDR[1:0] are ignored. The PSTRB[3:0] write strobe signals indicate which byte or bytes of the data bus contain valid data.

The following table shows the AHB5 TrustZone memory protection controller configuration registers.

Table 3.3. Registers
OFFSETNAMETYPERESETDESCRIPTION
0x000CTRLRW0x00000100

Bit[31] – Security lockdown

Bit[30:9] – Reserved

Bit[8] – Autoincrement

Reserved when BLK_SIZE > ADDR_WIDTH-11

Bit[7] – Data interface gating acknowledge (RO)

Reserved when GATE_PRESENT = 0

Bit[6] – Data interface gating request.

Reserved when GATE_PRESENT = 0

Bit[5] – Reserved

Bit[4] – Security error response configuration (CFG_SEC_RESP)

0:RAZ-WI

1: Bus Error

Bit[3:0] – Reserved

0x004-0x00CRSVDRO0x0Reserved
0x010BLK_MAXRO-Maximum value of block based index register
0x014BLK_CFGRO-

Bit[31] – Init in progress

Bit[30:4] - Reserved

Bit[3:0] – Block size

0: 32 Bytes

1: 64 Bytes

15: 1MByte

Block size = 1 << (BLK_CFG+5)

0x018BLK_IDXRW0x0

Index value for accessing block based look up table

Reserved when BLK_SIZE > ADDR_WIDTH-11.

The maximum value of BLK_IDX is defined by the BLK_MAX register.

0x01CBLK_LUT[n]RW

Implementation defined

Block based gating Look Up Table (LUT): Access to block based look up configuration space pointed to by BLK_IDX.

Bit[31:0] – each bit indicates one block:

If BLK_IDX is 0x0, bit[0] is block #0, bit[31] is block#31.

If BLK_IDX is 0x1, bit[0] is block #32, bit[31] is block#63.

If BLK_IDX is 0x2, bit[0] is block#64, bit[31] is block#95.

If BLK_IDX is 0xFFF, bit[0] is block#131040, bit[31] is block#131071.

The maximum value of BLK_IDX is defined by the BLK_MAX register.

For each configuration bit, 0 indicates secure, 1 indicates non-secure.

A full word write or read to this register automatically increments the BLK_IDX by one if enabled by CTRL[8].

The upper bits are reserved if BLK_SIZE > ADDR_WIDTH - 11.

0x020INT_STATRO0x00000000

bit[31:1] – Reserved

bit[0] – mpc_irq triggered

0x024INT_CLEARWO0x00000000

bit[31:1] – Reserved

bit[0] – mpc_irq clear (cleared automatically)

0x028INT_ENRW0x00000001

bit[31:1] - Reserved.

bit[0] – mpc_irq enable.

Enables interrupt output generation. The INT_STAT, INT_INFO1, and INT_INFO2 registers are still set for errors.

0x02CINT_INFO1RO0x00000000

haddr[31:0] of the first security violating address.

Bits are valid when mpc_irq is triggered. Subsequent security violationg transfers remain blocked, that is, not captured in this register and the register retains its value until mpc_irq is cleared.

0x030INT_INFO2RO0x00000000

Additional control bits of the first security violating transfer.

Bit [31:18] – Reserved

Bit [17] – cfg_ns

Bit [16] – hnonsec

Bit [15:0] - hmaster

Bits are valid when mpc_irq is triggered.

Subsequent security violating transfers remain blocked, that is, not captured in this register and the register retains its value until mpc_irq is cleared.

0x034INT_SETWO0x00000000

bit[31:1] – Reserved

bit[0] – mpc_irq set – Debug purpose only. Sets mpc_irq triggered in INT_STAT regardless of the mpc_irq_enable input.

0x0380xFCCRSVDRO0x0Reserved
0xFD0PIDR4RO0x04Peripheral ID 4 ([7:4] block count, [3:0] jep106_c_code)
0xFD4PIDR5RO0x00Peripheral ID 5 (not used)
0xFD8PIDR6RO0x00Peripheral ID 6 (not used)
0xFDCPIDR7RO0x00Peripheral ID 7 (not used)
0xFE0PIDR0RO0x60Peripheral ID 0 (Part number [7:0].)
0xFE4PIDR1RO0xB8Peripheral ID 1 ([7:4] jep106_id_3_0, [3:0] Part number[11:8])
0xFE8PIDR2RO0x1BPeripheral ID 2 ([7:4] revision, [3] jedec_used, [2:0] jep106_id_6_4)
0xFECPIDR3RO0x00Peripheral ID 3 ([7:4] ECO revision number, [3:0] customer modification number)
0xFF0CIDR0RO0x0DComponent ID 0
0xFF4CIDR1RO0xF0Component ID 1 (PrimeCell class)
0xFF8CIDR2RO0x05Component ID 2
0xFFCCIDR3RO0xB1Component ID 3

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