ICV_IGRPEN0, Interrupt Controller Virtual Interrupt Group 0 Enable register
The ICV_IGRPEN0 characteristics are:
Purpose
Controls whether virtual Group 0 interrupts are enabled or not.
Configuration
AArch32 System register ICV_IGRPEN0 bits [31:0] are architecturally mapped to AArch64 System register ICV_IGRPEN0_EL1[31:0] .
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
Attributes
ICV_IGRPEN0 is a 32-bit register.
Field descriptions
The ICV_IGRPEN0 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable |
Bits [31:1]
Reserved, RES0.
Enable, bit [0]
Enables virtual Group 0 interrupts.
| Enable | Meaning |
|---|---|
| 0b0 |
Virtual Group 0 interrupts are disabled. |
| 0b1 |
Virtual Group 0 interrupts are enabled. |
This field resets to 0.
Accessing the ICV_IGRPEN0
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| opc1 | opc2 | CRn | coproc | CRm |
|---|---|---|---|---|
| 0b000 | 0b110 | 0b1100 | 0b1111 | 0b1100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ICC_SRE.SRE == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then
return ICV_IGRPEN0;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.FMO == '1' then
return ICV_IGRPEN0;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.FIQ == '1' then
AArch32.TakeMonitorTrapException();
else
return ICC_IGRPEN0;
elsif PSTATE.EL == EL2 then
if ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.FIQ == '1' then
AArch32.TakeMonitorTrapException();
else
return ICC_IGRPEN0;
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
return ICC_IGRPEN0;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| opc1 | opc2 | CRn | coproc | CRm |
|---|---|---|---|---|
| 0b000 | 0b110 | 0b1100 | 0b1111 | 0b1100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ICC_SRE.SRE == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then
ICV_IGRPEN0 = R[t];
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.FMO == '1' then
ICV_IGRPEN0 = R[t];
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.FIQ == '1' then
AArch32.TakeMonitorTrapException();
else
ICC_IGRPEN0 = R[t];
elsif PSTATE.EL == EL2 then
if ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.FIQ == '1' then
AArch32.TakeMonitorTrapException();
else
ICC_IGRPEN0 = R[t];
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
ICC_IGRPEN0 = R[t];