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TLBI RVALE3IS, TLB Range Invalidate by VA, Last level, EL3, Inner Shareable

The TLBI RVALE3IS characteristics are:


If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

  • The entry is a stage 1 translation table entry, from any level of the translation table walk.

  • The entry would be used to translate the specified VA using the EL3 translation regime.

  • The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2^(5*SCALE +1) * Translation_Granule_Size)].

The invalidation only applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instruction.

The range of addresses invalidated is UNPREDICTABLE when:

  • For the 4K translation granule:

    • If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.

    • If TTL==10 and BaseADDR[20:12] is not equal to 000000000.

  • For the 16K translation granule:

    • If TTL==10 and BaseADDR[24:14] is not equal to 00000000000.
  • For the 64K translation granule:

    • If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.

    • If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.

For more information about the architectural requirements for this instruction see 'Invalidation of TLB entries from stage 2 translations' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.


This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI RVALE3IS are UNDEFINED.


TLBI RVALE3IS is a 64-bit System instruction.

Field descriptions

The TLBI RVALE3IS input value bit assignments are:


Bits [63:48]

Reserved, RES0.

TG, bits [47:46]

Translation granule size.




4K translation granule.


16K translation granule.


64K translation granule.

The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.

SCALE, bits [45:44]

The exponent element of the calculation that is used to produce the upper range.

NUM, bits [43:39]

The base element of the calculation that is used to produce the upper range.

TTL, bits [38:37]

TTL Level hint. The TTL hint is only guaranteed to invalidate entries in the range that match the level described by the TTL hint.


The entries in the range can be using any level for the translation table entries.


When using a 4KB or 64KB translation granule, all entries to invalidate are Level 1 translation table entries.

When using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00.


All entries to invalidate are Level 2 translation table entries.


All entries to invalidate are Level 3 translation table entries.

BaseADDR, bits [36:0]

The starting address for the range of the maintenance instruction.

When using a 4KB translation granule, this field is BaseADDR[48:12].

When using a 16KB translation granule, this field is BaseADDR[50:14].

When using a 64KB translation granule, this field is BaseADDR[52:16].

Executing the TLBI RVALE3IS instruction

Accesses to this instruction use the following encodings:


if PSTATE.EL == EL0 then
elsif PSTATE.EL == EL1 then
elsif PSTATE.EL == EL2 then
elsif PSTATE.EL == EL3 then