DCZID_EL0, Data Cache Zero ID register
The DCZID_EL0 characteristics are:
Purpose
Indicates the block size that is written with byte values of 0 by the DC ZVA (Data Cache Zero by Address) System instruction.
If ARMv8.5-MemTag is implemented, this register also indicates the granularity at which the DC GVA and DC GZVA instructions write.
Configuration
Attributes
DCZID_EL0 is a 64-bit register.
Field descriptions
The DCZID_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DZP | BS | |||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:5]
Reserved, RES0.
DZP, bit [4]
Data Zero Prohibited. This field indicates whether use of DC ZVA instructions is permitted or prohibited.
If ARMv8.5-MemTag is implemented, this field also indicates whether use of the DC GVA and DC GZVA instructions are permitted or prohibited.
DZP | Meaning |
---|---|
0b0 |
Instructions are permitted. |
0b1 |
Instructions are prohibited. |
The value read from this field is governed by the access state and the values of the HCR_EL2.TDZ and SCTLR_EL1.DZE bits.
BS, bits [3:0]
Log2 of the block size in words. The maximum size supported is 2KB (value == 9).
Accessing the DCZID_EL0
Accesses to this register use the following encodings:
MRS <Xt>, DCZID_EL0
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b0000 | 0b011 | 0b111 | 0b0000 |
if PSTATE.EL == EL0 then return DCZID_EL0; elsif PSTATE.EL == EL1 then return DCZID_EL0; elsif PSTATE.EL == EL2 then return DCZID_EL0; elsif PSTATE.EL == EL3 then return DCZID_EL0;