ICC_DIR_EL1, Interrupt Controller Deactivate Interrupt Register
The ICC_DIR_EL1 characteristics are:
Purpose
When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt.
Configuration
AArch64 System register ICC_DIR_EL1 performs the same function as AArch32 System register ICC_DIR.
Attributes
ICC_DIR_EL1 is a 64-bit register.
Field descriptions
The ICC_DIR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID | |||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:24]
Reserved, RES0.
INTID, bits [23:0]
The INTID of the interrupt to be deactivated.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
Accessing the ICC_DIR_EL1
There are two cases when writing to ICC_DIR_EL1 that were UNPREDICTABLE for a corresponding GICv2 write to GICC_DIR:
- When EOImode == 0. GICv3 implementations must ignore such writes. In systems supporting system error generation, an implementation might generate an SEI.
- When EOImode == 1 but no EOI has been issued. The interrupt will be de-activated by the Distributor, however the active priority in the CPU interface for the interrupt will remain set (because no EOI was issued).
Accesses to this register use the following encodings:
MSR ICC_DIR_EL1, <Xt>
| op0 | CRn | op1 | op2 | CRm |
|---|---|---|---|---|
| 0b11 | 0b1100 | 0b000 | 0b001 | 0b1011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if ICC_SRE_EL1.SRE == '0' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TDIR == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then
ICV_DIR_EL1 = X[t];
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then
ICV_DIR_EL1 = X[t];
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
ICC_DIR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if ICC_SRE_EL2.SRE == '0' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
ICC_DIR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
if ICC_SRE_EL3.SRE == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
ICC_DIR_EL1 = X[t];