ICH_EISR_EL2, Interrupt Controller End of Interrupt Status Register
The ICH_EISR_EL2 characteristics are:
Purpose
Indicates which List registers have outstanding EOI maintenance interrupts.
Configuration
AArch64 System register ICH_EISR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_EISR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
Attributes
ICH_EISR_EL2 is a 64-bit register.
Field descriptions
The ICH_EISR_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Status<n>, bit [n], for n = 0 to 15 | |||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:16]
Reserved, RES0.
Status<n>, bit [n], for n = 0 to 15
EOI maintenance interrupt status bit for List register <n>:
| Status<n> | Meaning |
|---|---|
| 0b0 |
List register <n>, ICH_LR<n>_EL2, does not have an EOI maintenance interrupt. |
| 0b1 |
List register <n>, ICH_LR<n>_EL2, has an EOI maintenance interrupt that has not been handled. |
For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all of the following are true:
- ICH_LR<n>_EL2.State is 0b00.
- ICH_LR<n>_EL2.HW is 0.
- ICH_LR<n>_EL2.EOI (bit [41]) is 1, indicating that when the interrupt corresponding to that List register is deactivated, a maintenance interrupt is asserted.
Otherwise the status bit takes the value 0.
Accessing the ICH_EISR_EL2
Accesses to this register use the following encodings:
MRS <Xt>, ICH_EISR_EL2
| op0 | CRn | op1 | op2 | CRm |
|---|---|---|---|---|
| 0b11 | 0b1100 | 0b100 | 0b011 | 0b1011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if ICC_SRE_EL2.SRE == '0' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ICH_EISR_EL2;
elsif PSTATE.EL == EL3 then
if ICC_SRE_EL3.SRE == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return ICH_EISR_EL2;