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IFSR32_EL2, Instruction Fault Status Register (EL2)

The IFSR32_EL2 characteristics are:

Purpose

Allows access to the AArch32 IFSR register from AArch64 state only. Its value has no effect on execution in AArch64 state.

Configuration

AArch64 System register IFSR32_EL2 bits [31:0] are architecturally mapped to AArch32 System register IFSR[31:0] .

If EL1 is AArch64 only, this register is UNDEFINED.

If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.

This register has no effect if EL2 is not enabled in the current Security state.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

IFSR32_EL2 is a 64-bit register.

Field descriptions

The IFSR32_EL2 bit assignments are:

When TTBCR.EAE == 0:
6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000000000000000FnV000ExT0FS[4]LPAE00000FS[3:0]

Bits [63:17]

Reserved, RES0.

FnV, bit [16]

FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.

FnVMeaning
0b0

IFAR is valid.

0b1

IFAR is not valid, and holds an UNKNOWN value.

This field is only valid for a synchronous External abort other than a synchronous External abort on a translation table walk. It is RES0 for all other Prefetch Abort exceptions.

This field resets to an architecturally UNKNOWN value.

Bits [15:13]

Reserved, RES0.

ExT, bit [12]

External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of External aborts.

In an implementation that does not provide any classification of External aborts, this bit is RES0.

For aborts other than External aborts this bit always returns 0.

This field resets to an architecturally UNKNOWN value.

Bit [11]

Reserved, RES0.

FS[4], bit [10]

This field is bit[4] of FS[4:0].

Fault Status bits. Bits [10] and [3:0] are interpreted together.

FSMeaning
0b00001

PC alignment fault.

0b00010

Debug exception.

0b00011

Access flag fault, level 1.

0b00101

Translation fault, level 1.

0b00110

Access flag fault, level 2.

0b00111

Translation fault, level 2.

0b01000

Synchronous External abort, not on translation table walk.

0b01001

Domain fault, level 1.

0b01011

Domain fault, level 2.

0b01100

Synchronous External abort, on translation table walk, level 1.

0b01101

Permission fault, level 1.

0b01110

Synchronous External abort, on translation table walk, level 2.

0b01111

Permission fault, level 2.

0b10000

TLB conflict abort.

0b10100

IMPLEMENTATION DEFINED fault (Lockdown fault).

0b11001

Synchronous parity or ECC error on memory access, not on translation table walk.

0b11100

Synchronous parity or ECC error on translation table walk, level 1.

0b11110

Synchronous parity or ECC error on translation table walk, level 2.

All other values are reserved.

When the RAS Extension is implemented, 0b11001, 0b11100, and 0b11110 are reserved.

The FS field is split as follows:

  • FS[4] is IFSR32_EL2[10].
  • FS[3:0] is IFSR32_EL2[3:0].

This field resets to an architecturally UNKNOWN value.

LPAE, bit [9]

On taking a Data Abort exception, this bit is set as follows:

LPAEMeaning
0b0

Using the Short-descriptor translation table formats.

0b1

Using the Long-descriptor translation table formats.

Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.

This field resets to an architecturally UNKNOWN value.

Bits [8:4]

Reserved, RES0.

FS[3:0], bits [3:0]

This field is bits[3:0] of FS[4:0].

See FS[4] for the field description.

When TTBCR.EAE == 1:
6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000000000000000FnV000ExT00LPAE000STATUS
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210

Bits [63:17]

Reserved, RES0.

FnV, bit [16]

FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.

FnVMeaning
0b0

IFAR is valid.

0b1

IFAR is not valid, and holds an UNKNOWN value.

This field is only valid for a synchronous External abort other than a synchronous External abort on a translation table walk. It is RES0 for all other Prefetch Abort exceptions.

This field resets to an architecturally UNKNOWN value.

Bits [15:13]

Reserved, RES0.

ExT, bit [12]

External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of External aborts.

In an implementation that does not provide any classification of External aborts, this bit is RES0.

For aborts other than External aborts this bit always returns 0.

This field resets to an architecturally UNKNOWN value.

Bits [11:10]

Reserved, RES0.

LPAE, bit [9]

On taking a Data Abort exception, this bit is set as follows:

LPAEMeaning
0b0

Using the Short-descriptor translation table formats.

0b1

Using the Long-descriptor translation table formats.

Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.

This field resets to an architecturally UNKNOWN value.

Bits [8:6]

Reserved, RES0.

STATUS, bits [5:0]

Fault status bits. All encodings not shown below are reserved:

STATUSMeaning
0b000000

Address size fault in TTBR0 or TTBR1.

0b000001

Address size fault, level 1.

0b000010

Address size fault, level 2.

0b000011

Address size fault, level 3.

0b000101

Translation fault, level 1.

0b000110

Translation fault, level 2.

0b000111

Translation fault, level 3.

0b001001

Access flag fault, level 1.

0b001010

Access flag fault, level 2.

0b001011

Access flag fault, level 3.

0b001101

Permission fault, level 1.

0b001110

Permission fault, level 2.

0b001111

Permission fault, level 3.

0b010000

Synchronous External abort, not on translation table walk.

0b010101

Synchronous External abort, on translation table walk, level 1.

0b010110

Synchronous External abort, on translation table walk, level 2.

0b010111

Synchronous External abort, on translation table walk, level 3.

0b011000

Synchronous parity or ECC error on memory access, not on translation table walk.

0b011101

Synchronous parity or ECC error on memory access on translation table walk, level 1.

0b011110

Synchronous parity or ECC error on memory access on translation table walk, level 2.

0b011111

Synchronous parity or ECC error on memory access on translation table walk, level 3.

0b100001

PC alignment fault.

0b100010

Debug exception.

0b110000

TLB conflict abort.

All other values are reserved.

When the RAS Extension is implemented, 0b011000, 0b011101, 0b011110, and 0b011111, are reserved.

The lookup level associated with a fault is:

  • For a fault generated on a translation table walk, the lookup level of the walk being performed.
  • For a Translation fault, the lookup level of the translation table that gave the fault. If a fault occurs because a stage of address translation is disabled, or because the input address is outside the range specified by the appropriate base address register or registers, the fault is reported as a fault at level 1.
  • For an Access flag fault, the lookup level of the translation table that gave the fault.
  • For a Permission fault, including a Permission fault caused by hierarchical permissions, the lookup level of the final level of translation table accessed for the translation. That is, the lookup level of the translation table that returned a Block or Page descriptor.

This field resets to an architecturally UNKNOWN value.

Accessing the IFSR32_EL2

Accesses to this register use the following encodings:

MRS <Xt>, IFSR32_EL2

op0CRnop1op2CRm
0b110b01010b1000b0010b0000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    return IFSR32_EL2;
elsif PSTATE.EL == EL3 then
    return IFSR32_EL2;
              

MSR IFSR32_EL2, <Xt>

op0CRnop1op2CRm
0b110b01010b1000b0010b0000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    IFSR32_EL2 = X[t];
elsif PSTATE.EL == EL3 then
    IFSR32_EL2 = X[t];
              


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