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MAIR_EL1, Memory Attribute Indirection Register (EL1)

The MAIR_EL1 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.

Configuration

AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PRRR[31:0] when TTBCR.EAE == 0.

AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MAIR0[31:0] when TTBCR.EAE == 1.

AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register NMRR[31:0] when TTBCR.EAE == 0.

AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register MAIR1[31:0] when TTBCR.EAE == 1.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

MAIR_EL1 is a 64-bit register.

Field descriptions

The MAIR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Attr7Attr6Attr5Attr4
Attr3Attr2Attr1Attr0
313029282726252423222120191817161514131211109876543210

MAIR_EL1 is permitted to be cached in a TLB.

Attr<n>, bits [8n+7:8n], for n = 0 to 7

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.

Attr is encoded as follows:

AttrMeaning
0b0000dd00Device memory. See encoding of 'dd' for the type of Device memory.
0b0000ddxx, (xx != 00)UNPREDICTABLE
0booooiiii, (oooo != 0000 and iiii != 0000)Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal Memory.
0b11110000Tagged Normal Memory. Inner+Outer Write-Back Non-Transient memory, Inner+Outer Read-Allocate, Inner+Outer Write-Allocate.
0bxxxx0000, (xxxx != 0000 and xxxx != 1111)UNPREDICTABLE

'dd' is encoded as follows:

dd | Meaning
0b00 | Device-nGnRnE memory
0b01 | Device-nGnRE memory
0b10 | Device-nGRE memory
0b11 | Device-GRE memory

'oooo' is encoded as follows:

'oooo'Meaning
0b0000See encoding of Attr
0b00RW, RW not 0b00Normal memory, Outer Write-Through Transient
0b0100Normal memory, Outer Non-cacheable
0b01RW, RW not 0b00Normal memory, Outer Write-Back Transient
0b10RWNormal memory, Outer Write-Through Non-transient
0b11RWNormal memory, Outer Write-Back Non-transient

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

'iiii' is encoded as follows:

'iiii'Meaning
0b0000See encoding of Attr
0b00RW, RW not 0b00Normal memory, Inner Write-Through Transient
0b0100Normal memory, Inner Non-cacheable
0b01RW, RW not 0b00Normal memory, Inner Write-Back Transient
0b10RWNormal memory, Inner Write-Through Non-transient
0b11RWNormal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in 'oooo' and 'iiii' fields have the following meanings:

R or WMeaning
0b0No Allocate
0b1Allocate

This field resets to an architecturally UNKNOWN value.

Accessing the MAIR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic MAIR_EL1 or MAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

MRS <Xt>, MAIR_EL1

op0CRnop1op2CRm
0b110b10100b0000b0000b0010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then
        return NVMem[0x140];
    else
        return MAIR_EL1;
elsif PSTATE.EL == EL2 then
    if HCR_EL2.E2H == '1' then
        return MAIR_EL2;
    else
        return MAIR_EL1;
elsif PSTATE.EL == EL3 then
    return MAIR_EL1;
              

MSR MAIR_EL1, <Xt>

op0CRnop1op2CRm
0b110b10100b0000b0000b0010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then
        NVMem[0x140] = X[t];
    else
        MAIR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
    if HCR_EL2.E2H == '1' then
        MAIR_EL2 = X[t];
    else
        MAIR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
    MAIR_EL1 = X[t];
              

MRS <Xt>, MAIR_EL12

op0CRnop1op2CRm
0b110b10100b1010b0000b0010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
        return NVMem[0x140];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.E2H == '1' then
    if PSTATE.EL == EL2 then
        return MAIR_EL1;
    elsif PSTATE.EL == EL3 then
        return MAIR_EL1;
else
    UNDEFINED;
              

MSR MAIR_EL12, <Xt>

op0CRnop1op2CRm
0b110b10100b1010b0000b0010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
        NVMem[0x140] = X[t];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.E2H == '1' then
    if PSTATE.EL == EL2 then
        MAIR_EL1 = X[t];
    elsif PSTATE.EL == EL3 then
        MAIR_EL1 = X[t];
else
    UNDEFINED;
              


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