MAIR_EL2, Memory Attribute Indirection Register (EL2)
The MAIR_EL2 characteristics are:
Purpose
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL2.
Configuration
AArch64 System register MAIR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HMAIR0[31:0] .
AArch64 System register MAIR_EL2 bits [63:32] are architecturally mapped to AArch32 System register HMAIR1[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
MAIR_EL2 is a 64-bit register.
Field descriptions
The MAIR_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| Attr7 | Attr6 | Attr5 | Attr4 | ||||||||||||||||||||||||||||
| Attr3 | Attr2 | Attr1 | Attr0 | ||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAIR_EL2 is permitted to be cached in a TLB.
Attr<n>, bits [8n+7:8n], for n = 0 to 7
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.
Attr is encoded as follows:
| Attr | Meaning |
|---|---|
| 0b0000dd00 | Device memory. See encoding of 'dd' for the type of Device memory. |
| 0b0000ddxx, (xx != 00) | UNPREDICTABLE |
| 0booooiiii, (oooo != 0000 and iiii != 0000) | Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal Memory. |
| 0b11110000 | Tagged Normal Memory. Inner+Outer Write-Back Non-Transient memory, Inner+Outer Read-Allocate, Inner+Outer Write-Allocate. |
| 0bxxxx0000, (xxxx != 0000 and xxxx != 1111) | UNPREDICTABLE |
'dd' is encoded as follows:
| dd | Meaning |
|---|
| 0b00 | Device-nGnRnE memory |
| 0b01 | Device-nGnRE memory |
| 0b10 | Device-nGRE memory |
| 0b11 | Device-GRE memory |
'oooo' is encoded as follows:
| 'oooo' | Meaning |
|---|---|
| 0b0000 | See encoding of Attr |
| 0b00RW, RW not 0b00 | Normal memory, Outer Write-Through Transient |
| 0b0100 | Normal memory, Outer Non-cacheable |
| 0b01RW, RW not 0b00 | Normal memory, Outer Write-Back Transient |
| 0b10RW | Normal memory, Outer Write-Through Non-transient |
| 0b11RW | Normal memory, Outer Write-Back Non-transient |
R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.
'iiii' is encoded as follows:
| 'iiii' | Meaning |
|---|---|
| 0b0000 | See encoding of Attr |
| 0b00RW, RW not 0b00 | Normal memory, Inner Write-Through Transient |
| 0b0100 | Normal memory, Inner Non-cacheable |
| 0b01RW, RW not 0b00 | Normal memory, Inner Write-Back Transient |
| 0b10RW | Normal memory, Inner Write-Through Non-transient |
| 0b11RW | Normal memory, Inner Write-Back Non-transient |
R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.
The R and W bits in 'oooo' and 'iiii' fields have the following meanings:
| R or W | Meaning |
|---|---|
| 0b0 | No Allocate |
| 0b1 | Allocate |
This field resets to an architecturally UNKNOWN value.
Accessing the MAIR_EL2
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic MAIR_EL2 or MAIR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
MRS <Xt>, MAIR_EL2
| op0 | CRn | op1 | op2 | CRm |
|---|---|---|---|---|
| 0b11 | 0b1010 | 0b100 | 0b000 | 0b0010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return MAIR_EL2;
elsif PSTATE.EL == EL3 then
return MAIR_EL2;
MSR MAIR_EL2, <Xt>
| op0 | CRn | op1 | op2 | CRm |
|---|---|---|---|---|
| 0b11 | 0b1010 | 0b100 | 0b000 | 0b0010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
MAIR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
MAIR_EL2 = X[t];
MRS <Xt>, MAIR_EL1
| op0 | CRn | op1 | op2 | CRm |
|---|---|---|---|---|
| 0b11 | 0b1010 | 0b000 | 0b000 | 0b0010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then
return NVMem[0x140];
else
return MAIR_EL1;
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '1' then
return MAIR_EL2;
else
return MAIR_EL1;
elsif PSTATE.EL == EL3 then
return MAIR_EL1;
MSR MAIR_EL1, <Xt>
| op0 | CRn | op1 | op2 | CRm |
|---|---|---|---|---|
| 0b11 | 0b1010 | 0b000 | 0b000 | 0b0010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then
NVMem[0x140] = X[t];
else
MAIR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '1' then
MAIR_EL2 = X[t];
else
MAIR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
MAIR_EL1 = X[t];