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RMR_EL3, Reset Management Register (EL3)

The RMR_EL3 characteristics are:

Purpose

If EL3 is the implemented and this register is implemented:

  • A write to the register at EL3 can request a Warm reset.
  • If EL3 can use AArch32 and AArch64, this register specifies the Execution state that the PE boots into on a Warm reset.

Configuration

AArch64 System register RMR_EL3 bits [31:0] are architecturally mapped to AArch32 System register RMR[31:0] when HaveEL(EL3).

When EL3 is implemented:

  • If EL3 can use AArch32 and AArch64 then this register must be implemented.
  • If EL3 cannot use AArch32 then it is IMPLEMENTATION DEFINED whether the register is implemented.

See the field descriptions for the reset values. These apply whenever the register is implemented.

Attributes

RMR_EL3 is a 64-bit register.

Field descriptions

The RMR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000000000000000000000000000000RRAA64
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

RR, bit [1]

Reset Request. Setting this bit to 1 requests a Warm reset.

This field resets to 0.

AA64, bit [0]

When EL3 can use AArch32, determines which Execution state the PE boots into after a Warm reset:

AA64Meaning
0b0

AArch32.

0b1

AArch64.

On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.

If EL3 cannot use AArch32 this bit is RAO/WI.

When implemented as a RW field, this field resets to 1 on a Cold reset.

Accessing the RMR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, RMR_EL3

op0CRnop1op2CRm
0b110b11000b1100b0100b0000
if PSTATE.EL == EL3 && IsHighestEL(EL3) then
    return RMR_EL3;
else
    UNDEFINED;
              

MSR RMR_EL3, <Xt>

op0CRnop1op2CRm
0b110b11000b1100b0100b0000
if PSTATE.EL == EL3 && IsHighestEL(EL3) then
    RMR_EL3 = X[t];
else
    UNDEFINED;
              


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